Electrical characteristics of CMOSFETs with gates crossing source/drain regions at 90/spl deg/ and 45/spl deg/

Abstract

The electrical characteristics of scaled CMOSFETs with gates crossing sources/drains at 90/spl deg/ and 45/spl deg/ are experimentally investigated using test devices fabricated by an n-well CMOS process with trench-isolation. The gain factors and the saturation drain-currents of n-MOSFETs are estimated by a simple correction theory which is derived by combining a center MOSFET and two edge MOSFETs. However, relatively large differences between the theoretical values and the experimental results are observed in p-MOSFETs with narrower widths less than the channel length. Other basic device parameters such as threshold voltages and subthreshold swings are qualitatively explained by the impurity profiles along the channel width direction, bird's beaks formed at the isolation-edges, and the change of channel length for narrow width 45/spl deg/ MOSFETs.