Defect parameter extraction in backend process steps using a multilayer checkerboard test structure

Abstract

To control defect appearance in numerous conducting layers of backend process steps, a novel multilayer checkerboard test structure (MCTS) is presented. The separation and localization of defects-causing electrically detectable intralayer short circuits as well as interlayer short circuits-is achieved by dividing the chip area into distinguishable small subchips inside given standard boundary pads without using any active semiconductor devices. The precise localization facilitates a versatile optical defect parameter extraction.