Use of SPIDER for the identification and analysis of process induced damage in 0.35 /spl mu/m transistors

Abstract

The paper presents a case study of the use of the SEMATECH SPIDER test structure to evaluate and identify critical damage producing plasma process steps in the fabrication of n- and p-MOS devices manufactured with a 0.35 /spl mu/m CMOS line with 6.5 nm oxide. Electrical characterization of transistor modules enabled the identification of contact etch step as the principal damage producing step for the technology under investigation. The results on HC reliability degradation in CMOS devices are in agreement with the direct observations of oxide degradation, showing that the nature of the damage is of the charging type.