{"title":"在CMOS工艺中互连电容的片上测量","authors":"A. Khalkhal, P. Nouet","doi":"10.1109/ICMTS.1995.513962","DOIUrl":null,"url":null,"abstract":"A new Test Structure for measurement of small constant capacitances is presented. As compared to previously published methods, improvements are obtained in the field of accuracy and resolution. No reference elements are used and the calculated capacitance is free of parasitic capacitance influence. Moreover, the Test Structure occupies a small area. It is particularly suitable for spatial scattering studies and for modelling of small dimension interconnect capacitances.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"On-chip measurement of interconnect capacitances in a CMOS process\",\"authors\":\"A. Khalkhal, P. Nouet\",\"doi\":\"10.1109/ICMTS.1995.513962\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new Test Structure for measurement of small constant capacitances is presented. As compared to previously published methods, improvements are obtained in the field of accuracy and resolution. No reference elements are used and the calculated capacitance is free of parasitic capacitance influence. Moreover, the Test Structure occupies a small area. It is particularly suitable for spatial scattering studies and for modelling of small dimension interconnect capacitances.\",\"PeriodicalId\":432935,\"journal\":{\"name\":\"Proceedings International Conference on Microelectronic Test Structures\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1995.513962\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1995.513962","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-chip measurement of interconnect capacitances in a CMOS process
A new Test Structure for measurement of small constant capacitances is presented. As compared to previously published methods, improvements are obtained in the field of accuracy and resolution. No reference elements are used and the calculated capacitance is free of parasitic capacitance influence. Moreover, the Test Structure occupies a small area. It is particularly suitable for spatial scattering studies and for modelling of small dimension interconnect capacitances.