A new hierarchical RSM for TCAD-based device design to predict CMOS development

Abstract

A new methodology in simulation-based CMOS process designs has been proposed, using a hierarchical RSM (Response Surface Method) and efficient experimental calibrations. The new design methodology has been verified in a half-micron CMOS process/device development using the test structure, which results in reliable prediction of the threshold voltage (Vth) and drain current (Ids) within 0.01 V and 0.84% errors, respectively. This method has also reduced simulation works to about one half required by the conventional RSM. TCAD based RSM is applied for predicting quarter-micron CMOS development.