{"title":"模拟CMOS技术中MOS失配的表征与建模","authors":"Shyh-Chyi Wong, J. Ting, S. Hsu","doi":"10.1109/ICMTS.1995.513967","DOIUrl":null,"url":null,"abstract":"This paper studies the mismatch characteristics in CMOS technology for precision analog design. Mismatch of MOS devices is investigated. The impact of layout-configuration and device-size are characterized. For clean mismatch measurement, a differential method of extracting mismatch parameters is developed. An empirical model is further proposed for simulating mismatch behavior in SPICE.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Characterization and modeling of MOS mismatch in analog CMOS technology\",\"authors\":\"Shyh-Chyi Wong, J. Ting, S. Hsu\",\"doi\":\"10.1109/ICMTS.1995.513967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper studies the mismatch characteristics in CMOS technology for precision analog design. Mismatch of MOS devices is investigated. The impact of layout-configuration and device-size are characterized. For clean mismatch measurement, a differential method of extracting mismatch parameters is developed. An empirical model is further proposed for simulating mismatch behavior in SPICE.\",\"PeriodicalId\":432935,\"journal\":{\"name\":\"Proceedings International Conference on Microelectronic Test Structures\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1995.513967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1995.513967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterization and modeling of MOS mismatch in analog CMOS technology
This paper studies the mismatch characteristics in CMOS technology for precision analog design. Mismatch of MOS devices is investigated. The impact of layout-configuration and device-size are characterized. For clean mismatch measurement, a differential method of extracting mismatch parameters is developed. An empirical model is further proposed for simulating mismatch behavior in SPICE.
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