Efficient extraction of metal parasitic capacitances

Abstract

Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed. Recommendations are made for optimum test structure design and it is indicated how such structures can provide an efficient means of assessing dielectric planarisation. This provides process engineers with a important, nondestructive means of assessing and monitoring a key technology parameter. The use of three-dimensional simulation in backend process optimisation is briefly described.