{"title":"不同间隔材料的LDD NMOSFET源极漏极漏电流","authors":"J. Om, M. Jo, Hyo-Sik Park, In-Sool Chung, W. Min","doi":"10.1109/ICMTS.1995.513968","DOIUrl":null,"url":null,"abstract":"The source/drain junction leakage currents of lightly doped drain (LDD) MOSFET for various gate sidewall spacer materials have been measured and analyzed. Since the step coverages of spacer materials and the etch rates of field oxide during the gate sidewall spacer etch process are different, the junction currents are found to be different for three spacer materials. Therefore, the corner defects formed at the boundaries between the source/drain substrate and the field oxide have different depth. The deeper the corner defects form, the more the junction leakage currents flow. The defects are generated by the damage from n/sup +/ source/drain As/sup 75/ implant process following the gate sidewall spacer etch.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Source/drain junction leakage current of LDD NMOSFET with various spacer materials\",\"authors\":\"J. Om, M. Jo, Hyo-Sik Park, In-Sool Chung, W. Min\",\"doi\":\"10.1109/ICMTS.1995.513968\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The source/drain junction leakage currents of lightly doped drain (LDD) MOSFET for various gate sidewall spacer materials have been measured and analyzed. Since the step coverages of spacer materials and the etch rates of field oxide during the gate sidewall spacer etch process are different, the junction currents are found to be different for three spacer materials. Therefore, the corner defects formed at the boundaries between the source/drain substrate and the field oxide have different depth. The deeper the corner defects form, the more the junction leakage currents flow. The defects are generated by the damage from n/sup +/ source/drain As/sup 75/ implant process following the gate sidewall spacer etch.\",\"PeriodicalId\":432935,\"journal\":{\"name\":\"Proceedings International Conference on Microelectronic Test Structures\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1995.513968\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1995.513968","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Source/drain junction leakage current of LDD NMOSFET with various spacer materials
The source/drain junction leakage currents of lightly doped drain (LDD) MOSFET for various gate sidewall spacer materials have been measured and analyzed. Since the step coverages of spacer materials and the etch rates of field oxide during the gate sidewall spacer etch process are different, the junction currents are found to be different for three spacer materials. Therefore, the corner defects formed at the boundaries between the source/drain substrate and the field oxide have different depth. The deeper the corner defects form, the more the junction leakage currents flow. The defects are generated by the damage from n/sup +/ source/drain As/sup 75/ implant process following the gate sidewall spacer etch.