R. Ott, H. Ollendorf, H. Lammering, T. Hladschik, W. Haensch
{"title":"An effective method to estimate defect limited yield impact on memory devices","authors":"R. Ott, H. Ollendorf, H. Lammering, T. Hladschik, W. Haensch","doi":"10.1109/ASMC.1999.798188","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798188","url":null,"abstract":"In this paper, we propose a new methodology to effectively reduce defect-related yield loss. We introduce a monitor system, in which defect data collected during the wafer processing is directly correlated to wafer test data. The amount of computed data is reasonable, it allows sample rates which are only limited by the inspection tool capacities. However, this new methodology provides accurate results on each individual wafer which is inspected inline. This enables detailed split lot analysis in real time and provides a defect related yield detractor pareto based on volume data.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Grindle, M. Bilodeau, M. Otis, J. Barnum, N. Tamayo, K. Bhattacharyya
{"title":"Evaluation of a fast defect detection tool to disposition product wafers with large defects in printed photoresist","authors":"S. Grindle, M. Bilodeau, M. Otis, J. Barnum, N. Tamayo, K. Bhattacharyya","doi":"10.1109/ASMC.1999.798243","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798243","url":null,"abstract":"Summary form only given. KLA-Tencor has installed a new, fast, 50 micron defect detection tool on line at IBM Burlington, staffed by IBM and KLA-Tencor engineers and operators. The KT2401 simultaneously scans entire wafers while storing and presenting a pass/fail recommendation to the operator for review. The KT2401 is used in combination with optical microscope review stations to disposition wafers and diagnose root causes of defects. We evaluated the capability of the KT2401 to: 1) randomly sample the range of products and photo levels; 2) gauge the defects from a targeted tool set; 3) gauge the defects from a targeted process point; 4) quantify the population of photolithography process defects. We describe the potential for process improvements provided by use of the KT2401 by quantifying the rate of rework, the types of defects found, and root causes identified.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127855444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"In situ dielectric etch process technology for advanced leading edge production worthy etch applications","authors":"Jian Ding, P. Arleo, J. Hasselbach","doi":"10.1109/ASMC.1999.798211","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798211","url":null,"abstract":"In situ integrated dielectric etch processes are developed for advanced applications, such as self aligned contact and dual damascene structures, in the inductively coupled parallel plate semiconducting chamber. The integrated, in situ process steps include BARC opening, oxide or low k etch with high etch rate and high selectivity to nitride, resist/polymer strip, and nitride removal. This in situ capability will provide significant productivity benefits for structures that require multiple sequential process steps typically involving multiple chambers or systems.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116752308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Contact and non contact post-CMP cleaning of thermal oxide silicon wafers","authors":"N. Moumen, M. Guarrera, C. Piboontum, A. Busnaina","doi":"10.1109/ASMC.1999.798236","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798236","url":null,"abstract":"Post-CMP cleaning of polished thermal oxide wafers is conducted using megasonic and brush cleaning techniques. The wafers were polished using Rodel silica based slurry. The results achieved by the two different cleaning methods are presented and compared. They show that although the two techniques produce comparable cleaning performance, non-contact cleaning using SCl produces lower defect counts on the cleaned wafers.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121509683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Lin, C. Marcadal, S. Ganguli, Bo Zheng, J. Schmitt, Ling Chen
{"title":"Characterization of copper CVD process by a process monitor","authors":"K. Lin, C. Marcadal, S. Ganguli, Bo Zheng, J. Schmitt, Ling Chen","doi":"10.1109/ASMC.1999.798310","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798310","url":null,"abstract":"The mass spectrometric technique for monitoring copper chemical vapor deposition process using Cu(hfac)(tmvs) has been investigated. Characterization of the process chemistry identified the main ionic species that could be used to monitor and study the process. Reactant flow rate and the mass spectrometric signal of TMVS was found to have linear relationship. The process monitor response time for the reactants and the product species was of the order of seconds. The reproducibility of the Cu CVD process was studied by using a process-monitoring recipe. This process monitoring technique has been used for tool and process optimization.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125669875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementing state of the art advanced process control and factory automation solutions at White Oak Semiconductor","authors":"T. Urenda, T. Dowd, K. Dimond, B. Schulze","doi":"10.1109/ASMC.1999.798192","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798192","url":null,"abstract":"This paper describes the partnership SEMY Engineering, Inc. and White Oak Semiconductor formed to successfully provide automation and advanced process control (APC) solutions from a combination of proprietary and commercially available software systems. The White Oak factory objective was to implement a computer integrated manufacturing (CIM) system providing full availability of all necessary data for yield analysis and process control. Semiconductor production throughput and reliability at White Oak has significantly increased using this implementation. A large ROI (>500%) has already been realized in the lithography cell in the first year alone.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131537715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Shallow trench isolation etch process for 0.2 /spl mu/m trench capacitor DRAM technology","authors":"Y. Karzhavin","doi":"10.1109/ASMC.1999.798233","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798233","url":null,"abstract":"This paper presents results of the STI etch process developed for 64 MB Trench Capacitor DRAM technology, scalable for future generations of the product as well. An aspect ratio of 2.5 was achieved. High uniformity of the trench depths and after etch Critical Dimensions (ACI CD) are demonstrated. A low etch bias <0.01 /spl mu/m was achieved. This manufacturable STI process for sub-0.2 /spl mu/m technologies was developed for applications in an MRlE etcher with an electrostatic chuck (ESC) and Silicon shadow ring. The Si-ring provided 60-100% improvement in the STI depth and ACI CD stability across the wafer. Mean time between chamber cleans and cost of the process kit consumable parts improved 30 - 50%.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127748396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interconnect constraints on BEOL manufacturing","authors":"R. Mangaser, C. Mark, Kenneth Rose","doi":"10.1109/ASMC.1999.798251","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798251","url":null,"abstract":"As CMOS devices are scaled to deep submicron dimensions, BEOL manufacturability will be constrained by both global and short local interconnects. The constraints on BEOL manufacturability imposed by linewidth variability, random defects, signal integrity, and electromigration are considered for 250 and 180 nm technology. Our 250 nm projections are based on available information about Intel's 250 nm Katmai microprocessor. This design has been extended to 180 nm by doubling logic and memory. We find that signal integrity is the greatest constraint and this could be alleviated by going to copper technology.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133772996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Yield methodology-three phases approach","authors":"T. Pouedras, M. Ben-tzur","doi":"10.1109/ASMC.1999.798171","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798171","url":null,"abstract":"A novel yield methodology approach is developed. This methodology is applicable to each of the three phases from technology development to manufacturing. This methodology highlights the goals for each phase and describes all the procedures needed for optimizing the learning rate and reducing the cycle time between technology development and manufacturing.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131130265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Sturm, F. Frauenhoffer, J. Dorner, O. Kirschenhofer, T. Reisinger
{"title":"Advanced WIP control for make-to-order wafer fabrication","authors":"R. Sturm, F. Frauenhoffer, J. Dorner, O. Kirschenhofer, T. Reisinger","doi":"10.1109/ASMC.1999.798176","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798176","url":null,"abstract":"This paper gives an overview of advanced scheduling and dispatching policies for WIP (work in process) management within the wafer fabrication process. Additionally, the pros and cons of general WIP control philosophies are opposed. Several control policies are evaluated for the application in complex make-to-order environment such as ASIC production. Based on the real shop floor environment of Philips SMST and the currently used control policies a proposal is presented answering the following two questions: what are the requirements of tomorrow's WIP control systems applied in make-to-order wafer fabrication; and how can these control policies be implemented and introduced on the shop floor using existing WIP control and scheduling systems?.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121249293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}