10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)最新文献

{"title":"Exhaust deposit clean process using a remote NF/sub 3/ plasma (MAC-ICP)","authors":"E. Sanchez, S. Li, H. Ho, B. Bul, Yu Chang, Chiliang Chen, D. Foxhoven, S. Chen, K. Littau, I. Beinglass","doi":"10.1109/ASMC.1999.798208","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798208","url":null,"abstract":"Polysilicon deposition process byproducts in the form of exhaust powder deposits present time consuming and periodic maintenance that includes manual cleaning of exhaust components. A technology was therefore developed that allows a dramatic reduction in mean time between cleans thereby significantly increasing uptime of polysilicon deposition tools. Powder deposits and accompanying adsorbed gases throughout the entire exhaust line down to the pump inlet and silencer are cleaned in-situ, without trapping, by reacting with fluorine radicals from a remote NF/sub 3/ plasma. A novel compact remote plasma unit-a magnetically coupled inductively coupled plasma (MAC-ICP)-was developed for this immediate purpose and successfully integrated into the existing single-wafer polysilicon deposition system. The evaluation, optimization, automation, and process integration of the cleaning technique is presented.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114831339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Throughput monitoring to track and improve semiconductor lithography equipment performance","authors":"H. Magoon, P. H. Mitchell","doi":"10.1109/ASMC.1999.798180","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798180","url":null,"abstract":"A key goal in semiconductor manufacturing is continuous improvement in fabricator throughput and increased production equipment efficiency. This goal must be achieved at minimum cost and without negatively affecting process capability or equipment reliability. Throughput monitoring is an excellent way to track equipment productivity and highlight changes in equipment performance. This paper describes the development of an automated throughput monitoring technique which compares equipment throughput to a standard and identifies specific throughput components requiring corrective action. This method is applicable to a wide range of semiconductor equipment. As a specific example, this method was applied to a set of ten state-of-the-art steppers.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"24 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116782344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenging the paradigm of monitor reduction to achieve lower product costs","authors":"R. Williams, D. Gudmundsson, R. Nurani, M. Stoller, A. Chatterjee, S. Seshadri, J. Shanthikumar","doi":"10.1109/ASMC.1999.798306","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798306","url":null,"abstract":"Increasing competition within the semiconductor industry is forcing many manufacturers to consider and implement aggressive cost reduction measures across many operations. In addition, defect inspection steps are often perceived as being \"non-value add\" metrology operations, and are frequently the primary focus for further monitor reduction and/or elimination to reduce operational costs. In this paper, the highlights of a joint research project between Intel Corporation and KLA-Tencor Corporation are discussed, with the primary focus on the use of advanced statistical and stochastic models that utilize defect, yield, and financial inputs to hilly characterize the overall costs associated with the monitoring and control of random defect excursions in an advanced semiconductor manufacturing process. The use of the KLA-Tencor Sample Planner/sup TM/ program provides a sophisticated methodology to evaluate the overall cost impacts associated with proposed monitor reduction and monitor elimination activities. The analysis illustrated the importance of assessing the yield impact due to defect excursions when pursuing further monitor reduction and/or elimination. In addition, the project results confirmed that the current inspection sampling plan that was being utilized by Intel (with minor modifications), provided a cost-effective allocation of the existing defect inspection capacity. Consequently, the Sample Planner program proved to be an effective tool in challenging the paradigm of monitor reduction to achieve lower product costs in an advanced semiconductor manufacturing line.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122498437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Semiconductor and spending outlook: slow recovery underway and fundamental changes underfoot","authors":"C. J. Fuhs","doi":"10.1109/ASMC.1999.798166","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798166","url":null,"abstract":"In the aftermath of the financial crisis, chip manufacturers appear to be getting healthier, but are still cautious in capital spending as the oversupply conditions in the industry appear to be lingering. While the \"technology buying\" mode is still is place, some parts of the world are beginning to spend on capacity again. Is this trend toward capacity buying to continue? When will the inflection point occur for the industry to enter the next boom? What is the impact of the industry's transition to the 128-Mbit DRAM in light of Rambus' failure to develop the market this year? What is the outlook for end-market demand for semiconductors? Will fabless semiconductor companies face another capacity shortage? The author presents Dataquest's outlook and forecasts for these markets, and present details about industry capacity and the likely road to recovery. In addition the competitive dynamics in the chip world have changed dramatically over the last several years. Fuhs explores the key reasons for these changes and how they could affect the manufacturing infrastructure in the next decade and directions technology trends may or may not accelerate.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124554773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of a new laser scanning pattern wafer inspection tool to leading edge memory and logic applications at Infineon Technologies","authors":"T. Reuter, U. Bohmler, S. Steck, M. Mclaren, Siqun Xiao, R. Howland Pinto","doi":"10.1109/ASMC.1999.798253","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798253","url":null,"abstract":"A new patterned wafer laser-based inspection tool has been introduced to the market place, incorporating double darkfield laser scanning technology. Developed from a well-known production-proven platform, the new system is intended to provide the sensitivity required for 0.18 /spl mu/m design rules, with extendibility to 0.13 /spl mu/m. The inspection technology combines low angle laser illumination with dual darkfield scattered light collection channels. Enhancements to the illumination and collection optics have allowed for improved defect sensitivity and capture; and enhanced software algorithms have provided greater compensation for process variation, further increasing defect capture. The sensitivity performance and production worthiness of the tool were evaluated at Siemens Microelectronics Centre and the key results are presented. Both memory and logic products were evaluated, including memory products with 0.2 /spl mu/m design rule, and logic products with 0.2 /spl mu/m design rule. Layers from the front-end and back-end of the manufacturing process were evaluated. On memory products, sensitivity to defects occurring during capacitor and isolation trench formation was demonstrated, including etch defects deep in the trench structures and sub 0.1 /spl mu/m discrepancies in the formation of isolation trenches. Results from post-metal etch inspection demonstrated enhanced sensitivity in both array and periphery regions, largely achieved by exploiting the new ability to perform region-based optimisation, allowing full die area inspections. On logic products, surface foreign material less than 0.1 /spl mu/m in diameter was detected amidst logic structures and, in the same inspection pass, etch residuals affecting the memory cache area were also captured. The machine was installed and operated in a high capacity wafer production environment and adhered to all specified throughput, up-time and reliability matrices throughout the evaluation period.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115452760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A quantitative approach for minimizing fab cost of ownership through systems integration","authors":"T. Colvin, J. Rayter, I. Paprotny, G. Mackulak","doi":"10.1109/ASMC.1999.798190","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798190","url":null,"abstract":"The design of a semiconductor fab is a complex problem. Market competition, subsequent reduced product margins, and a heightened interest in cost of ownership (COO) have added additional dimensions. We propose a quantitative method for analyzing total system design tradeoffs. The key to this approach is designed flexibility. We propose that additional up front expenditure for flexibility allows for extended facility life and reduced total life cycle cost. A hypothetical comparison illustrates that from 1.5%-3.5% in annual savings result from an additional 10% initial investment, if the facility life can be extended five additional years.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130399010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Alignment optimization and residual analysis for critical DUV photolithography","authors":"C. Putnam, J. Tyminski, R. Batterson, A. Gallo","doi":"10.1109/ASMC.1999.798269","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798269","url":null,"abstract":"This work examines the alignment residual data for photolithography imaging in relationship to the maximum-minimum measured overlay values with linear factors corrected. Within the scope of this work, the relationships of maximum and minimum overlay vectors are examined instead of a three-sigma value characterizing the overlay. (The maximum vector is very close to a three sigma number, and the effective analysis would not be very different if three-sigma metric had been considered.) Such evaluation can lead to the understanding of what levels of alignment residuals are required to meet corresponding overlay budgets. It can be used to choose the alignment strategy or as a filter of real-time production alignment data.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132063237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tool capacity improvement through specialization of operator activities","authors":"J. Foster, J. Hennessy","doi":"10.1109/ASMC.1999.798220","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798220","url":null,"abstract":"This paper is a case study illustrating the success of re-deploying a subset of operators to perform specialized tasks to recoup tool capacity. In a large fabricator, where the same tool type is distributed across the floor, and where WIP must be transported by hand to the next tool set(s), operator availability at tools is often compromised. Previous observation studies at a large fabricator measured significant (magnitudes in this paper are normalized to protect the confidentiality of the client) capacity loss on Wet tools due to \"Wait for Operator\". The plan for the project was to achieve higher and more consistent operator coverage at Wet tools by re-deploying a subset of the department's headcount to perform the WIP transportation. The goal of the project was to show an increase (in actuality a reclamation) of overall tool capacity, through better operator coverage of the tools. Better operator coverage (with the same number of operators) would be achieved by shifting a subset of operator workload to a dedicated subset of operators. Throughout a 6-week period of essentially constant throughput, the increase in capacity was measured by a combination of throughput and cycle time improvements.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114712644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}