10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)最新文献

Analysis and reduction of defects induced by in-line wafer probing 在线晶圆探测缺陷的分析与减少

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798255

M. Polavarapu, J. Peters, S. Wright

引用次数: 0

WSi/sub x//poly-Si gate stack etching for advanced dRAM applications 用于先进dRAM应用的WSi/sub //多晶硅栅极堆栈刻蚀

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798235

F. Leverd, L. Loisil, T. Lill, J. Trevor, P. Van Holt, L. Van Autryve, T. Varga, J. Chinn

引用次数: 1

Haystack syndrome avoidance on massive correlation for probe vs. E-test data through the concurrent use of tree base models and trellis graphics. Application on sub-micron mix-signal product for the determination of the best process conditions for yield maximisation 通过同时使用树基模型和网格图形避免探测与E-test数据大量相关的干草堆综合征。在亚微米混合信号产品上的应用，以确定收率最大化的最佳工艺条件

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798185

C. Ortega, J. Ignacio Alonso, E. Sobrino, J. Bonal

{"title":"Haystack syndrome avoidance on massive correlation for probe vs. E-test data through the concurrent use of tree base models and trellis graphics. Application on sub-micron mix-signal product for the determination of the best process conditions for yield maximisation","authors":"C. Ortega, J. Ignacio Alonso, E. Sobrino, J. Bonal","doi":"10.1109/ASMC.1999.798185","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798185","url":null,"abstract":"In an environment which requires an intensive capitalisation like the semiconductor industry, time-detection/time-reaction to any kind of yield degradation is a key issue. Abundant literature covers the existent methodologies and strategies to prevent, detect and react to the cosmetic defects. Even hardware solutions are available in the market which offer the possibility through product or control inspections to monitor them for the analysis of electrical measurements, performed at the end of the process sequence, and their relationships with yield predictors. The analysis of hundred of variables associated with a yield descriptor presents an important challenge from the statistical standpoint. We have developed a solution that allows an easier differentiation of the main contributor variables to the yield descriptor explanation as well as a graphical output of the analysis. The graphical output also includes the concept of multivariate analysis. Multivariate analysis accounts for the relationships of several different variables against each other. Trellis library provides excellent graphical solutions to this type of analysis.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Application of ADC techniques to characterize yield-limiting defects identified with the overlay of E-test/inspection data on short loop process testers 应用ADC技术表征短回路过程测试仪上e测试/检测数据叠加识别的产量限制缺陷

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798258

T. Henry, O. Patterson, G. Brown

引用次数: 3

Cycle time and bottleneck analysis 周期时间和瓶颈分析

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798179

W. Laure

引用次数: 6

Ensemble average laser light scattering (EALLS)-an effective alternative to particle counting for monitoring turbidity in ultrapure water [for semiconductor rinsing] 集合平均激光散射(EALLS)-监测超纯水浊度的粒子计数的有效替代方法[用于半导体冲洗]

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798203

A. Banerjee, M. Lambertson, D. Scarpine

引用次数: 1

Concept and initial feasibility of contamination TCAD by integration with commercial software 与商业软件集成的污染TCAD的概念和初步可行性

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798307

J. Hofmeister, H. Parks, B. Vermeire, Z. Murshalin, R. Graves, peixiong zhao, K. Galloway

{"title":"Concept and initial feasibility of contamination TCAD by integration with commercial software","authors":"J. Hofmeister, H. Parks, B. Vermeire, Z. Murshalin, R. Graves, peixiong zhao, K. Galloway","doi":"10.1109/ASMC.1999.798307","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798307","url":null,"abstract":"Flexible manufacturing of ICs depends on technology computer-aided design (TCAD) tools. As ICs scale, contamination effects become more significant. Metal ions are a major source of poor electrical performance in solid state devices causing increased junction leakage, oxide breakdown strength degradation and metal-oxide-semiconductor (MOS) capacitor leakage which adversely affect the function of ultra large scale integrated (ULSI) circuits. It is important to know the level of contamination that is low enough to be acceptable for a particular application and how effective the wafer cleaning strategies are. There is a need for TCAD tools that include microcontamination effects to produce viable processes for the deep submicron era. This paper describes a concept for integrating contamination effects into the Silvaco VWF Software for the specific case of metals deposited from process solutions. Initial feasibility of the concept is demonstrated by comparison of experimental results from devices fabricated with an intentionally contaminated process with results from simulations for that process.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129601754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Real time failure analysis of Cu interconnect defectivity through bitmap overlay analysis 基于位图叠加分析的铜互连缺陷实时失效分析

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798169

V. Sheth, H. Nguyen, P. Dao, A.M. Miscione

引用次数: 0

Minimizing in-line calculated yield errors by optimizing and maintaining ADC classifier performance 通过优化和维持ADC分类器的性能，最大限度地减少在线计算的产量误差

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798256

J. Blais, T. Pilon, C. Robitaille, K. Bartholomew, V. Fischer

{"title":"Minimizing in-line calculated yield errors by optimizing and maintaining ADC classifier performance","authors":"J. Blais, T. Pilon, C. Robitaille, K. Bartholomew, V. Fischer","doi":"10.1109/ASMC.1999.798256","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798256","url":null,"abstract":"Automatic defect classification (ADC) has become a standard tool to monitor and manage yield-limiting defects in the semiconductor industry. The ADC system is more productive than manual classification systems because of its greater accuracy, consistency, and throughput. Engineers have used it to assist in yield learning, monitoring for excursions, and making in-line yield predictions. Semiconductor manufactures use in-line yield predictions to adjust wafer starts and appropriately disposition lots. This paper explores the quality of the in-line defect-limited yield (DLY) prediction as a function of ADC system performance. When the ADC system is operating optimally, the in-line DLY error is minimized. Maintaining optimal system performance is a two-part project. First, system hardware must be appropriately calibrated and maintained. Secondly, the ADC classifier set-ups must be optimized. ADC classifier performance is measured with two values: accuracy and purity. The relationship between accuracy, purity, and error in the PLY calculation is described. Techniques to optimize classifier performance are discussed. Programmed defect standard wafers (PDSW) are a proven means to monitor the health of inspection tools. A particular PDSW, known as TDS, provides benefits over conventional PDSWs in that it may be used on a variety of inspection tools and is a challenging and sensitive measure of ADC performance. The improvement of in-line defect-limited yield caused by the implementation of the TDS is explored. The impact of in-line DLY prediction on overall fabricator productivity is also discussed.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Process equipment architecture definition using desktop throughput simulation 使用桌面吞吐量模拟处理设备架构定义

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798197

H.R. Carvalheira, D.V. Putnam-Pite, T.E. Kane, T. Tracey, K.R. Benjamin

引用次数: 0