Real time failure analysis of Cu interconnect defectivity through bitmap overlay analysis

Abstract

Bitmap to in-line defect overlay analysis was performed on a 4 Mbit SRAM memory array, which uses copper interconnect. This analysis provides an effective method of identifying killer copper defects, which inhibit product yield. It has been shown that bitmap overlay (BMOL) analysis is a very effective way of identifying killer defects for any technology at any process step. This can be proven to be a very powerful tool to relate physical defectivity to significant yield loss mechanisms. It has been shown that BMOL can be used to assign a root cause mechanism or a defect to an actual electrical fail without incurring tedious hours of destructive failure analysis. Failure analysis was, however, used to initially verify and confirm root cause of the electrical failures identified by BMOL analysis.