WSi/sub x//poly-Si gate stack etching for advanced dRAM applications

Abstract

Results of a tungsten silicide/poly-Si gate etch process based on a Cl/sub 2//NF/sub 3//HBr silicide step are presented. The addition of fluorine to the main etch suppresses the formation of polymers in the reactor chamber. HBr allows the control of the sidewall passivation of the microstructures. A very thin yet robust sidewall layer is desired to achieve ultimate critical dimension (CD) control without sacrificing profile shape. CD microloading (i.e. the difference in the CD bias for nested and isolated lines) is minimized by operating at elevated cathode temperatures. The grain structure of the silicide film determines the roughness of the silicon etch front prior to approaching the gate oxide. In-situ reflectometry and atomic force microscopy have been used to analyse the mechanism of gate oxide texturing and punch through. Reflectometry can be used to predict the exposure of the gate oxide and to switch early enough to a very selective etch step that clears the poly-Si.