10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)最新文献_第3页

Use of multiple lithography monitors in a defect control strategy for high volume manufacturing 在大批量生产的缺陷控制策略中使用多个光刻监视器

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798240

L. Bond, D. Sutton, K. Turnquest

{"title":"Use of multiple lithography monitors in a defect control strategy for high volume manufacturing","authors":"L. Bond, D. Sutton, K. Turnquest","doi":"10.1109/ASMC.1999.798240","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798240","url":null,"abstract":"As I-line and deep ultraviolet (DUV) photolithography processes grow more complex, yield improvement has become more challenging and critical. With the advent of smaller sub-micron geometries using newer chemically amplified photoresists, a high sensitivity, easy to review and trouble-shoot monitor is essential. In order to fully understand what defects may be generated by a process or process tool, it is necessary to fully duplicate the given process on the test wafer used to monitor the defect level. That concept is called: Process Induced Defects Per Wafer Pass (PIDPWP). PIDPWP requires the real and exact product process to be used in creating the defect test monitor. To monitor a photolithography process using the concept of PIDPWP, typically, a coat, expose, and develop sequence is used with a selected and simplified mask, such as a diffraction grating. In a manufacturing area with multiple technologies, each step of the process may require different resist/developer combinations. Each resist/developer combination requires constant monitoring to insure adequately low levels of defects. Our solution to this problem is to use multiple integrated monitors to verify each process. This allows for better response time and defect density control when the defects are due to the chemicals or chemical delivery systems, and not just the mechanical aspects of the tool. In addition, we have designed our system to have minimal impact on production, yet still allow for statistical process control, analysis, and defect reduction. The Photo Track Monitor (PTM) methods and results of this control strategy as applied in a high volume manufacturing environment are discussed.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"14 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113935841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Effects of in-situ arsenic-doped amorphous silicon emitter process on SiGe heterojunction bipolar transistors 原位砷掺杂非晶硅发射极工艺对SiGe异质结双极晶体管的影响

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798264

M. Gallagher, M. Rice, G. Langdeau, L. Lanzerotti, M. Dupuis, R. Johnson, L. Stern, E. Sanchez, C. Chen

引用次数: 0

Advanced interconnect process development utilizing wafer inspection with "on-the-fly" automatic defect classification 先进的互连工艺开发利用晶圆检测与“即时”自动缺陷分类

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798239

A. Skumanich, J. Boyle, D. Brown

{"title":"Advanced interconnect process development utilizing wafer inspection with \"on-the-fly\" automatic defect classification","authors":"A. Skumanich, J. Boyle, D. Brown","doi":"10.1109/ASMC.1999.798239","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798239","url":null,"abstract":"Wafer inspection providing classified defect density with \"on-the-fly\" automatic defect classification (OTF-ADC) is increasingly being utilized to obtain the detailed defect information for rapid resolution of defectivity issues. The OTF-ADC defect categories allow the critical defect types to be segregated and tracked during the actual wafer inspection without any throughput reduction. Inspection with OTF-ADC can be utilized at various interconnect steps such as post-develop, post-etch, and post-metal-CMP step for advanced process development and line monitoring. Significant benefits are realized with early defect excursion detection by tracking the classified defect counts instead of simply the total defect counts. An associated requirement is the ability to capture all of the relevant defect types at key inspection points. Utilizing the Applied Materials WF736 with a combined bright-field and dark-field architecture, the full range of yield limiting defects was captured at two key interconnect stages: post litho, and post CMP. After-development inspection (ADI) with the WF found both macro (>15 um) and micro (<15 u) defects. In some instances, the micro-defects could only be imaged with a SEM. The OTF-ADC provided good accuracy for both ADI and CMP. Using an example from post metal CMP, OTF-ADC is shown to identify hidden excursions which would have had significant yield impact and which would have gone undetected with standard \"total count\" inspection methods. The use of OTF-ADC provides improved time-to-information and enhances the yield potential by permitting defect sourcing which facilitates corrective action.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115327930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Correlation of ellipsometric volume fraction to polysilicon grain size from transmission electron microscopy 透射电镜下椭偏体积分数与多晶硅晶粒尺寸的关系

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798265

T. A. Carbone, P. Plourde, E. Karagiannis

引用次数: 4

Dual frequency silicon nitride film of low thermal budget for pre-metal dielectric applications in sub-0.25 /spl mu/m devices 用于低于0.25 /spl μ m器件的金属前介质低热预算双频氮化硅薄膜

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798303

Yuxiang Wang, J. Lee, B. Thakur, J. Huang

引用次数: 7

Total operational efficiency (TOE): the determination of two capacity and cycle time components and their relationship to productivity improvements in a semiconductor manufacturing line 总操作效率(TOE):确定半导体生产线的两个容量和周期时间组件及其与生产率改进的关系

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798177

D. Martin

{"title":"Total operational efficiency (TOE): the determination of two capacity and cycle time components and their relationship to productivity improvements in a semiconductor manufacturing line","authors":"D. Martin","doi":"10.1109/ASMC.1999.798177","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798177","url":null,"abstract":"Short cycle time manufacturing (SCM) concepts have been developed to help understand and manage the performance of a manufacturing line. SCM assumes that each tool/toolset (and hence the overall line) can be described by a performance curve that relates cycle time to throughput, with cycle time increasing non-linearly as throughput approaches capacity. Productivity improvements are realized by reducing the components of capacity loss, which increases the overall capacity and, thus, shifts the performance curve. To implement SCM, all major components of capacity loss must be defined, including the primary driver for cycle time: idle-no-WIP. In order to achieve this, the analysis must look beyond a strictly tool-centric focus to a system view focus so that the interaction between the tool, operator, work-in-progress, etc., can be included in the components of capacity loss. This paper develops and explains total operational efficiency (TOE), which is a key component of SCM. TOE describes the capacity and cycle time components of a tool/toolset in a self-consistent and hierarchical way that reflect a system level view and where the interaction of the tool, operator, WIP, etc., are taken into account. Once these components and their relationship have been defined, it is then possible to more clearly articulate responsible owners and assess the possibility of improvement. The reality of most semiconductor manufacturing lines is that tool availability is rarely the largest detractor from capacity. Instead, other issues such as the amount of automation, line layout, cycle time requirements, technology mix, etc., become the prime determiners of the effective capacity. In addition, TOE enables meaningful comparisons to be made between different lines and for the better tracking of improvements over time in any given line on a component by component basis.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126941618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Interconnect technology and design implications for future ASIC and system-on-a-chip (SOC) implementations 未来ASIC和片上系统(SOC)实现的互连技术和设计含义

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798213

R. Gutmann, K. Chan, R. Graves

引用次数: 0

Cost effective reticle quality management strategies in wafer fabs 在晶圆厂的成本效益的网线质量管理策略

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798238

W. Tomlinson, V. Samek, B. Shiffler, D. Gudmundsson, J. Merritt, R. Nurani, J. Shanthikumar

引用次数: 5

Minimizing the cost of low K dielectric manufacturing implementation 降低低K介电介质制造实现的成本

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798304

W. Rowe, J. Braley, D. Frye, M. E. Mills

{"title":"Minimizing the cost of low K dielectric manufacturing implementation","authors":"W. Rowe, J. Braley, D. Frye, M. E. Mills","doi":"10.1109/ASMC.1999.798304","DOIUrl":"https://doi.org/10.1109/ASMC.1999.798304","url":null,"abstract":"The integration of organic low k interconnection dielectric materials into wafer fab manufacturing processes requires changes to the equipment set and the process sequence. The capital investment required for conversion and the impact of the new equipment and materials on the finished wafer cost are a concern to wafer manufacturers. We have modeled the costs of converting 180 nm logic/microprocessor fabs from Al/W/SiO/sub 2/ and Cu/SiO/sub 2/ dual damascene interconnect processes to Al/W/Low-k and Cu/Low-k processes. Equipment was chosen to minimize the capital outlay required for conversion. The output of the models includes equipment capital requirements: changes to staffing and facilities costs, and the cost of finished wafers. Our results indicate that conversion to low k processing should require only modest capital expenditures and effects the finished wafer costs by less that 5%. For example, one case study shows 10% of a fab's capacity could be converted from Al/W/SiO/sub 2/ interconnect technology to Al/W/Low-k by the addition of a wafer apply track. In this case wafers with the Al/W/Low-k interconnection technology are produced in a new fab at a lower cost than those with Al/W/SiO/sub 2/ interconnection technology.","PeriodicalId":424267,"journal":{"name":"10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114382006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Predicting failing bitmap signatures for memory arrays with critical area analysis 预测失效位图签名的内存阵列与关键区域分析

10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295) Pub Date : 1999-09-08 DOI: 10.1109/ASMC.1999.798216

J. Segal, T. Ho, B. Hodgkins, P. Mišić, J. Lin, Mohan Yegnashankaran

引用次数: 4