Shallow trench isolation etch process for 0.2 /spl mu/m trench capacitor DRAM technology

Abstract

This paper presents results of the STI etch process developed for 64 MB Trench Capacitor DRAM technology, scalable for future generations of the product as well. An aspect ratio of 2.5 was achieved. High uniformity of the trench depths and after etch Critical Dimensions (ACI CD) are demonstrated. A low etch bias <0.01 /spl mu/m was achieved. This manufacturable STI process for sub-0.2 /spl mu/m technologies was developed for applications in an MRlE etcher with an electrostatic chuck (ESC) and Silicon shadow ring. The Si-ring provided 60-100% improvement in the STI depth and ACI CD stability across the wafer. Mean time between chamber cleans and cost of the process kit consumable parts improved 30 - 50%.