An effective method to estimate defect limited yield impact on memory devices

Abstract

In this paper, we propose a new methodology to effectively reduce defect-related yield loss. We introduce a monitor system, in which defect data collected during the wafer processing is directly correlated to wafer test data. The amount of computed data is reasonable, it allows sample rates which are only limited by the inspection tool capacities. However, this new methodology provides accurate results on each individual wafer which is inspected inline. This enables detailed split lot analysis in real time and provides a defect related yield detractor pareto based on volume data.