Interconnect constraints on BEOL manufacturing

Abstract

As CMOS devices are scaled to deep submicron dimensions, BEOL manufacturability will be constrained by both global and short local interconnects. The constraints on BEOL manufacturability imposed by linewidth variability, random defects, signal integrity, and electromigration are considered for 250 and 180 nm technology. Our 250 nm projections are based on available information about Intel's 250 nm Katmai microprocessor. This design has been extended to 180 nm by doubling logic and memory. We find that signal integrity is the greatest constraint and this could be alleviated by going to copper technology.