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Continuously auto-tuned and self-ranged dual-path PLL design with hybrid AFC 带混合AFC的连续自调谐自量程双路锁相环设计
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783227
Min Wang, Bo Zhou, W. Rhee, Zhihua Wang
{"title":"Continuously auto-tuned and self-ranged dual-path PLL design with hybrid AFC","authors":"Min Wang, Bo Zhou, W. Rhee, Zhihua Wang","doi":"10.1109/ICICDT.2011.5783227","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783227","url":null,"abstract":"This paper describes a dual-path phase locked loop (PLL) design which automatically tunes to capture the desired frequency as well as the input control voltage range of the dual-path LC voltage-controlled oscillator (VCO). A hybrid automatic frequency calibration (AFC) circuit provides digital frequency calibration and mixed-mode continuous frequency tuning. Since the hybrid AFC circuit independently controls the coarse-tuning control voltage of VCO in this structure, the VCO input control voltage range can be preset before the PLL is locked. Therefore, an optimum loop filter voltage range can be chosen to have good charge pump matching or VCO gain linearity. Simulation results verify that the self-ranged control can be achieved by adjusting the output range of the limiting amplitude amplifier (LAA) during the PLL transient mode.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 8-bit 50-Msamples/s switched-current pipelined ADC with residue generator and interlaced stage 一个8位50 m采样/s的开关电流流水线ADC，带有残留发生器和隔行级
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783226
Guo-Ming Sung, Ying-Tzu Lai
{"title":"A 8-bit 50-Msamples/s switched-current pipelined ADC with residue generator and interlaced stage","authors":"Guo-Ming Sung, Ying-Tzu Lai","doi":"10.1109/ICICDT.2011.5783226","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783226","url":null,"abstract":"This paper presents a 8-bit 50-MHz sampling rate switched-current pipelined analog-to-digital converter (ADC) in a standard 0.35-μm 2P4M CMOS process. Not only a new residue generator is proposed to cancel the sub-DAC circuit, but also an interlaced arrangement is adopted to improve the transmission error in a seven-stage pipelined ADC. That is, the odd stage adopts the traditional structure and the even stage employs the proposed residue generator. The simulated results reveal that power dissipation is 160mW and sampling rate is 50 MHz at a supply voltage of 3.3 V. As a sinusoidal waveform with 1 MHz sampling rate is adopted, a signal to noise distortion ratio (SNDR) of 48 dB and an effective number of bits (ENOB) of 7.7 bits are demonstrated. Additionally, the differential nonlinearity (DNL) of −0.4 LSB ∼ +0.3 LSB and the integral nonlinearity (INL) of −0.7 LSB ∼ +0.8 LSB are presented with a chip area of roughly 1.59 × 1.63 mm2.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evolution of embedded flash memory technology for MCU 单片机嵌入式快闪存储技术的发展
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783209
H. Hidaka
{"title":"Evolution of embedded flash memory technology for MCU","authors":"H. Hidaka","doi":"10.1109/ICICDT.2011.5783209","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783209","url":null,"abstract":"Embedded flash memory technology has undergone tremendous growth of demands with various performance requirements driven by expanded applications of MCU (Micro Controller Unit) products. High temperature operations with highest reliability for auto-motive applications, very low power embedded EEPROM functions for smart-cards, and ultra low-voltage operations for medical applications are driving factors in developing embedded flash technologies. Together with evolving memory cell technology, resolving performance/power trade-offs by developing dedicated design platforms with optimized eFlash technology, memory interface & bus designs, and the whole chip design methodologies, has realized advanced MCU products line-ups by split-gate MONOS flash technology with a wide range of applied products including auto-motive and security applications.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115276763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Time and workload dependent device variability in circuit simulations 电路仿真中与时间和工作负载相关的器件可变性
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783193
D. Rodopoulos, S. Mahato, V. V. de Almeida Camargo, B. Kaczer, F. Catthoor, S. Cosemans, G. Groeseneken, A. Papanikolaou, D. Soudris
{"title":"Time and workload dependent device variability in circuit simulations","authors":"D. Rodopoulos, S. Mahato, V. V. de Almeida Camargo, B. Kaczer, F. Catthoor, S. Cosemans, G. Groeseneken, A. Papanikolaou, D. Soudris","doi":"10.1109/ICICDT.2011.5783193","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783193","url":null,"abstract":"Simulations of an inverter and a 32-bit SRAM bit slice are performed based on an atomistic approach. The circuits' devices are populated with individual defects, which have realistic carrier-capture and emission behaviour. The wide distribution of defect time scales, accounts for both fast (Random Telegraph Noise - RTN) and near-permanent (Bias Temperature Instability - BTI) defects. The atomistic property of the model allows the detection of workload dependency in the delay of both circuits.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"16 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Timing error prevention using elastic clocking 使用弹性时钟防止定时错误
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783192
Kwanyeob Chae, Chang-Ho Lee, S. Mukhopadhyay
{"title":"Timing error prevention using elastic clocking","authors":"Kwanyeob Chae, Chang-Ho Lee, S. Mukhopadhyay","doi":"10.1109/ICICDT.2011.5783192","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783192","url":null,"abstract":"“Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking. Time borrowing allows a pipeline to compensate the timing slack by borrowing time from the next pipeline stage and clock stretching pays back the borrowed time to the next pipeline stage. Thus, a system employing such dynamic timing control technique can prevent errors with a small performance penalty and eventually operate without safety margin. The net effect is better power-performance trade-off under voltage scaling i.e. lower power consumption for a target frequency or higher operating frequency for a target power. The proposed technique was validated using a prototype test-chip designed in 180-nm CMOS technology.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123803942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
On the magnitude of Random telegraph noise in ultra-scaled MOSFETs 超大尺度mosfet中随机电报噪声的大小研究
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783191
K. Cheung, J. Campbell
{"title":"On the magnitude of Random telegraph noise in ultra-scaled MOSFETs","authors":"K. Cheung, J. Campbell","doi":"10.1109/ICICDT.2011.5783191","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783191","url":null,"abstract":"Random telegraph noise (RTN) has been shown to be a more severe scaling issue than the Random Dopant Effect (RDE). However this observation relies heavily on studies which focus only on threshold voltage (VTH) fluctuations. VTH measurements make separation of these two scaling issues (RTN and RDE) difficult. Since future scaled devices may use channels with no or low doping, it is important to examine the impact of RTN without the influence of RDE. In this work, we experimentally verify the “hole in the inversion layer” model of RTN and then use it to examine the magnitude of RTN in ultra-scaled devices without the influence of RDE. This analysis strongly suggests that RTN is a serious issue even in the absence of RDE.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128584878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Beta-Matrix ESD network: Throughout end of placement rules? β -矩阵ESD网络:整个放置结束规则?
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783235
J. Bourgeat, P. Galy, B. Jacquier
{"title":"Beta-Matrix ESD network: Throughout end of placement rules?","authors":"J. Bourgeat, P. Galy, B. Jacquier","doi":"10.1109/ICICDT.2011.5783235","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783235","url":null,"abstract":"Electrostatic Discharge (ESD) protection for advanced CMOS technologies is based on efficient device Network. But these protection strategies imply some constraint on IO and particularly on the frame and the placement in IO ring. In this context we develop and propose an ESD network with Beta-Matrix power device and its own trigger circuit which are integrated in each IO. We obtain a new local strategy which allows removing all IO placement constraint.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116147602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low power embedded memory design – process to system level considerations 低功耗嵌入式存储器设计过程对系统级的考虑
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783221
E. Terzioglu, S. Yoon, C. Jung, Ritu Chaba, Venu Boynapalli, M. Abu-Rahma, Joseph Wang, Sam Yang, G. Nallapati, A. Thean, C. Chidambaram, M. Han, G. Yeap, M. Sani
{"title":"Low power embedded memory design – process to system level considerations","authors":"E. Terzioglu, S. Yoon, C. Jung, Ritu Chaba, Venu Boynapalli, M. Abu-Rahma, Joseph Wang, Sam Yang, G. Nallapati, A. Thean, C. Chidambaram, M. Han, G. Yeap, M. Sani","doi":"10.1109/ICICDT.2011.5783221","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783221","url":null,"abstract":"Embedded memories are widely used in low power System-on-Chip (SoC) applications. Low power performance can be optimized with process, circuits, architecture and system level co-development. In this paper, low power design considerations are described in advanced technology nodes to address memory leakage and active power dissipation. Memory bit cell design in context of process technology definition, circuit techniques at the macro design level, and chip-level integration considerations for low power are described.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116818586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electrical characteristic fluctuation of 16 nm MOSFETs induced by random dopants and interface traps 随机掺杂剂和界面陷阱诱导的16nm mosfet电特性波动
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783187
Hui-Wen Cheng, Y. Chiu, Yiming Li
{"title":"Electrical characteristic fluctuation of 16 nm MOSFETs induced by random dopants and interface traps","authors":"Hui-Wen Cheng, Y. Chiu, Yiming Li","doi":"10.1109/ICICDT.2011.5783187","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783187","url":null,"abstract":"In this paper, we estimate the influences of random dopants (RDs) and interface traps (ITs) using experimentally calibrated 3D device simulation on electrical characteristics of high-κ / metal gate CMOS devices. Statistically random devices with 2D ITs between the interface of silicon and HfO2 film as well as 3D RDs inside the device channel are simulated. Fluctuations of threshold voltage and on-/off-state current for devices with different effective oxide thickness of insulator film are analyzed and discussed. The engineering findings significantly indicate that RDs and ITs govern characteristics, respectively, are statistically correlate to each other and RDs dominate device's variability, compared with the influence of ITs; however, the influence degree varies with IT's number, density and position. The effect of RDs and ITs on device characteristic should be considered together properly. Notably, the position of ITs and RDs results in very different fluctuation in spite of the same number of ITs and RDs.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134290138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
3D integrable nanowire FET sensor with intrinsic sensitivity boost 具有内在灵敏度提升的三维可积纳米线场效应管传感器
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783190
C. O. Chui, J. Kina, K. Shin
{"title":"3D integrable nanowire FET sensor with intrinsic sensitivity boost","authors":"C. O. Chui, J. Kina, K. Shin","doi":"10.1109/ICICDT.2011.5783190","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783190","url":null,"abstract":"In this paper, we review a recently developed transformative nanowire FET sensor concept and 3D-compatible fabrication technology. Compared to the generic nanowire FET sensors, an intrinsic boost in detection sensitivity is accomplished through the seamless integration of a sensing nanowire with an amplifying nanowire FET. Exclusively enabled by top-down nanofabrication technology, the back-end-of-line compatible sub-450 °C manufacturing processes have been developed. Sensing experimental data have also revealed around 1 order of magnitude sensitivity improvement in solution pH detection. Finally, an ultra-low thermal budget nanowire formation technology has been preliminarily developed for future 3D integration with CMOS.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128423374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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