Low power embedded memory design – process to system level considerations

Abstract

Embedded memories are widely used in low power System-on-Chip (SoC) applications. Low power performance can be optimized with process, circuits, architecture and system level co-development. In this paper, low power design considerations are described in advanced technology nodes to address memory leakage and active power dissipation. Memory bit cell design in context of process technology definition, circuit techniques at the macro design level, and chip-level integration considerations for low power are described.