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2011 IEEE International Conference on IC Design & Technology最新文献

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Through Silicon Via technology using tungsten metallization 通过硅通孔技术采用钨金属化
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783204
G. Pares, N. Bresson, S. Minoret, V. Lapras, P. Brianceau, J. Lugand, R. Anciant, N. Sillon
{"title":"Through Silicon Via technology using tungsten metallization","authors":"G. Pares, N. Bresson, S. Minoret, V. Lapras, P. Brianceau, J. Lugand, R. Anciant, N. Sillon","doi":"10.1109/ICICDT.2011.5783204","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783204","url":null,"abstract":"Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking), or MEMS structure packaging. Different alternatives are currently investigated such as via-first or via-last. Into the via-first family two different approaches can be considered. The TSV's can be done before the FEOL (pre-process approach) or in-between the FEOL and the BEOL (mid process approach). Each solution has advantages and drawbacks depending on the final application in particular. In a first part of this paper the tungsten mid-process TSV technology will be presented and briefly compared to the copper mid-process approaches. Then, the process of the tungsten TSV fabrication will be detailed and morphological characterizations will be presented. We will focus on two specific parts of the process which have been specifically optimized for the tungsten TSV technology: the low temperature insulation oxide and the tungsten deposition-etch back sequence to fill the vias. The results of those optimizations will be presented and discussed. Last, we will introduce the electrical test vehicle used in this work and present the main results regarding via resistances. Some specific recommendations will by proposed in term of design and integration rules in relation with the process constraints.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A low jitter active body-biasing control-based output buffer in 65nm PD-SOI 基于65nm PD-SOI的低抖动有源体偏置控制输出缓冲器
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783232
Dimitri Soussan, S. Majcherczak, A. Valentian, M. Belleville
{"title":"A low jitter active body-biasing control-based output buffer in 65nm PD-SOI","authors":"Dimitri Soussan, S. Majcherczak, A. Valentian, M. Belleville","doi":"10.1109/ICICDT.2011.5783232","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783232","url":null,"abstract":"This paper proposes a specific low jitter and high speed Ouput interface which takes advantage of the Partially Depleted Silicon-on-Insulator technology while avoiding its drawbacks related to floating body effects. Thanks to an active body-biasing control technique, the additional jitter related to PD-SOI history effect, as well as the higher static leakage current compared to bulk technology, are more than compensated. In depth analyses are presented to highlight the robustness of this technique with respect to the other solutions considering various capacitive loads and temperatures.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129932706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Balanced Truncation of a stable non-minimal deep-submicron CMOS interconnect 稳定非最小深亚微米CMOS互连的平衡截断
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783206
A. Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs
{"title":"Balanced Truncation of a stable non-minimal deep-submicron CMOS interconnect","authors":"A. Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs","doi":"10.1109/ICICDT.2011.5783206","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783206","url":null,"abstract":"As the widening of process variability in submicron CMOS technology calls for accurate timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. In this context, model order reduction techniques have been used extensively to reduce the complexity of extracted interconnect circuits and to expedite fast and accurate circuit simulation. In the interconnect modeling, solving large-scale Lyapunov equations arises as a necessity in model order reduction techniques based on Balanced Truncation. In this paper, within this framework, dominant eigensubspaces of the product of the system Gramians are approximated directly. We construct orthogonal basis sets for the dominant subspaces of controllability and observability Gramians and perform eigenvalue decomposition to reduce the cost of singular value decomposition. As the experimental results indicate, the proposed approach can significantly reduce the complexity of interconnect, while retaining high accuracy in comparison to the original model.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Smart stackingTM technology: An industrial solution for 3D layer stacking 智能堆叠tm技术:3D层堆叠的工业解决方案
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783202
C. L. Blanchard, I. Radu, M. Sadaka, K. Landry
{"title":"Smart stackingTM technology: An industrial solution for 3D layer stacking","authors":"C. L. Blanchard, I. Radu, M. Sadaka, K. Landry","doi":"10.1109/ICICDT.2011.5783202","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783202","url":null,"abstract":"Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low temperature direct bonding and wafer thinning (figure 1). This technology is adapted for advanced semiconductor applications such as Back Side Illumination (BSI) CMOS Image Sensors (CIS) as well as 3D integration approaches [1,2].","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127893400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new prediction model for effects of plasma-induced damage on parameter variations in advanced LSIs 等离子体损伤对晚期lsi参数变化影响的新预测模型
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783213
K. Eriguchi, Y. Takao, K. Ono
{"title":"A new prediction model for effects of plasma-induced damage on parameter variations in advanced LSIs","authors":"K. Eriguchi, Y. Takao, K. Ono","doi":"10.1109/ICICDT.2011.5783213","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783213","url":null,"abstract":"This paper proposes a physics-based variability prediction model integrating the effects of plasma-induced damage (PID) in advanced LSIs. We focus on charging damage to high-k gate dielectrics and physical damage (Si recess by ion bombardment). In addition to gate length-variation which has been discussed so far as a dominant factor for (static) variability, we demonstrate how PID impacts on – increases – the parameter variation (e.g., σVth), by employing both experimental PID data for high-k and Si substrate damage and a Monte Carlo method. The model prediction suggests a considerable increase in parameter variations by PID such as threshold voltage and off-state leakage.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133327748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Layout optimization to maximize tolerance in SEILA: Soft error immune latch 布局优化，以最大限度地容忍在SEILA:软误差免疫闩锁
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783238
T. Uemura, T. Sakoda, H. Matsuyama
{"title":"Layout optimization to maximize tolerance in SEILA: Soft error immune latch","authors":"T. Uemura, T. Sakoda, H. Matsuyama","doi":"10.1109/ICICDT.2011.5783238","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783238","url":null,"abstract":"The purpose of this paper is optimization of layout on soft error immune latch (SEILA) for maximizing soft-error mitigation efficiency, and investigating mechanisms of charge collection on multi-node and discussing layout dependence on soft-error. We evaluate soft-error rate (SER) on un-robust latch, conventional robust latch, SEILA with changing well structure, distances from well-contacts, and distance between soft-error critical nodes through neutron acceleration experiments at Osaka Univ. Soft-error mitigation efficiency awfully change with changing layout. In designing robust latches, it is most important for high the mitigation to separated critical nodes with STI and we need to take care on layout especially distance between critical nodes.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131308898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Scaled nanoelectromechanical (NEM) hybrid devices 纳米机电(NEM)混合器件
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783242
H. Mizuta, M. García-Ramírez, Z. Moktadir, Y. Tsuchiya, S. Sawai, J. Ogi, S. Oda
{"title":"Scaled nanoelectromechanical (NEM) hybrid devices","authors":"H. Mizuta, M. García-Ramírez, Z. Moktadir, Y. Tsuchiya, S. Sawai, J. Ogi, S. Oda","doi":"10.1109/ICICDT.2011.5783242","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783242","url":null,"abstract":"This paper overviews recent attempts at co-integrating nano-electro-mechanical systems (NEMS) with nanoelectronic devices aiming to add more functionalities to conventional Si devices in ‘More-than-Moore’ domain and also explore novel physical principles in ‘Beyond CMOS’ domain.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114528690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications 65nm PD-SOI无故障保持触发器，用于MTCMOS电源开关应用
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783222
J. Le-Coz, P. Flatresse, S. Clerc, M. Belleville, A. Valentian
{"title":"65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications","authors":"J. Le-Coz, P. Flatresse, S. Clerc, M. Belleville, A. Valentian","doi":"10.1109/ICICDT.2011.5783222","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783222","url":null,"abstract":"This work presents a partially depleted Silicon-on-Insulator (PD-SOI) low-static power consumption Retention Flip-Flop (REFF). This flip-flop is designed in order to avoid wake-up transient glitches. In addition specific leakage reduction techniques are used to compensate the extra leakage currents induced by the SOI floating body effects. This leads to a static power consumption reduced by 2 for only 6% of extra silicon area, compared to a regular floating body implementation.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"122 3S1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124594820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a low-cost floating-point programmable vertex processor for mobile graphics applications based on hybrid number system 基于混合数字系统的低成本浮点可编程顶点处理器的设计
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783231
Shen-Fu Hsiao, Chan-Feng Chiu, Chia-Sheng Wen
{"title":"Design of a low-cost floating-point programmable vertex processor for mobile graphics applications based on hybrid number system","authors":"Shen-Fu Hsiao, Chan-Feng Chiu, Chia-Sheng Wen","doi":"10.1109/ICICDT.2011.5783231","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783231","url":null,"abstract":"Recent OpenGL ES 2.0 API Specification for embedded systems graphics operations requires programmable vertex shader and fragment shader to process vertex and pixel data. Calculation of dot-product for two vectors and transcendental functions for a scalar are two fundamental arithmetic operations in the vertex processing. Since some complicated arithmetic operations in binary number system (BNS) turn into simple operations of addition and/or multiplication in the logarithmic number system (LNS), we present a low-cost design of a floating-point programmable vertex processor based on hybrid BNS and LNS. The proposed design achieves at least the same (or even higher) precision with much lower cost compared with recent similar implementations.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129709059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
TSV number minimization using alternative paths 使用备选路径最小化TSV数量
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783203
Chun-Hua Cheng, Chih-Hsien Kuo, Shih-Hsu Huang
{"title":"TSV number minimization using alternative paths","authors":"Chun-Hua Cheng, Chih-Hsien Kuo, Shih-Hsu Huang","doi":"10.1109/ICICDT.2011.5783203","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783203","url":null,"abstract":"In a three-dimensional integrated circuit (3D IC) design, through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic for 3D IC design. In this paper, we point out that there often exist idle functional units and idle TSVs at each control step. If we use idle functional units and idle TSVs to form an alternative path to replace direct TSVs for data transfer, the number of TSVs can be reduced. Based on that observation, we present an ILP (integer linear programming) approach to formally draw up our problem. Given a high-level synthesis result and a clock period constraint, we perform post-processing to fully utilize alternative paths for TSV number minimization. Compared with previous work that minimizes the TSV number without considering alternative paths, experimental results show that our approach can further reduce 16.92% TSV number without affecting the circuit performances.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127446774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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