65nm PD-SOI无故障保持触发器，用于MTCMOS电源开关应用

2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI:10.1109/ICICDT.2011.5783222

J. Le-Coz, P. Flatresse, S. Clerc, M. Belleville, A. Valentian

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引用次数: 1

摘要

这项工作提出了一种部分耗尽的绝缘体上硅(PD-SOI)低静态功耗保持触发器(REFF)。这个触发器的设计是为了避免唤醒瞬态故障。此外，还采用了特殊的泄漏减少技术来补偿由SOI浮体效应引起的额外泄漏电流。与常规的浮动体实现相比，这使得静态功耗降低了2%，仅增加了6%的硅面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications

This work presents a partially depleted Silicon-on-Insulator (PD-SOI) low-static power consumption Retention Flip-Flop (REFF). This flip-flop is designed in order to avoid wake-up transient glitches. In addition specific leakage reduction techniques are used to compensate the extra leakage currents induced by the SOI floating body effects. This leads to a static power consumption reduced by 2 for only 6% of extra silicon area, compared to a regular floating body implementation.

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2011 IEEE International Conference on IC Design & Technology

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