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2011 IEEE International Conference on IC Design & Technology最新文献

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A single TSV-rail 3D quasi delay insensitive asynchronous signaling 单TSV-rail三维准延迟不敏感异步信令
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783201
M. Belleville, E. Beigné, A. Valentian
{"title":"A single TSV-rail 3D quasi delay insensitive asynchronous signaling","authors":"M. Belleville, E. Beigné, A. Valentian","doi":"10.1109/ICICDT.2011.5783201","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783201","url":null,"abstract":"Asynchronous communications are foreseen as mandatory for implementing 3D multiple tiers circuits. The drawback of asynchronous rails compared to synchronous ones is the higher number of interconnects. This number needs to be decreased when horizontal interconnects are replaced by Through Silicon Vias (TSV) because of their big silicon footprint. A circuit using only one TSV for asynchronous, quasi delay insensitive 3D signal propagation is proposed. This achieves to save two TSVs out of three, while offering 1Gbits/s capability.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123232210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An on-chip waveform capturer for diagnosing off-chip power delivery 用于诊断片外电力输送的片上波形捕获器
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783194
K. Yoshikawa, T. Hashida, M. Nagata
{"title":"An on-chip waveform capturer for diagnosing off-chip power delivery","authors":"K. Yoshikawa, T. Hashida, M. Nagata","doi":"10.1109/ICICDT.2011.5783194","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783194","url":null,"abstract":"In-place diagnosis of off-chip power delivery resonance is demonstrated with on-chip waveform capturer and power delivery network (PDN) exciter that were prototyped in a 65 nm CMOS technology. Oscillatory waveforms are captured after the excitation of PDN, from which an LCR lumped equivalent circuit of PDN seen by on-chip circuits is algorithmically derived. The consistency of component values is confirmed among the demonstrated in-place diagnosis and full-wave analysis.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116305000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Statistical delay calculation with Multiple Input Simultaneous Switching 多输入同步切换的统计延迟计算
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783205
Qin Tang, A. Zjajo, Michel Berkelaar, Nick van der Meijs
{"title":"Statistical delay calculation with Multiple Input Simultaneous Switching","authors":"Qin Tang, A. Zjajo, Michel Berkelaar, Nick van der Meijs","doi":"10.1109/ICICDT.2011.5783205","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783205","url":null,"abstract":"The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical analysis method to capture statistical gate delay variations, able to accurately handle MISS. Experiment results obtained with a 45nm technology show that our approach accurately obtains not only mean and standard deviation, but also the third moment, skewness.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127558813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Separation of NBTI component from channel hot carrier degradation in pMOSFETs focusing on recovery phenomenon pmosfet中NBTI元件与通道热载流子降解的分离，重点研究恢复现象
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783215
Y. Mitani, S. Fukatsu, D. Hagishima, K. Matsuzawa
{"title":"Separation of NBTI component from channel hot carrier degradation in pMOSFETs focusing on recovery phenomenon","authors":"Y. Mitani, S. Fukatsu, D. Hagishima, K. Matsuzawa","doi":"10.1109/ICICDT.2011.5783215","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783215","url":null,"abstract":"Channel hot-carrier (CHC) degradation becomes more critical as the channel length is reduced. In general, CHC degradation is evaluated using DC stress applying both gate and drain bias. However, in the case of p-channel MOSFETs, negative bias temperature instabilities (NBTI) also degrades threshold voltage (VTH) and saturation drain current (Isat) under DC stress applying gate bias. Therefore, CHC degradation might include the NBTI component, which would lead to over-estimate the CHC degradation. Therefore, a separation of the BTI component from CHC degradation is necessary to predict device lifetime more accurately. In this study, a simple separation method of NBTI and CHC component from CHC test data is proposed, focusing on the recovery phenomenon, which is a distinctive behavior of NBTI.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130693541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Gate-driven 3.3V ESD clamp using 1.8V transistors 栅极驱动3.3V ESD钳使用1.8V晶体管
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783234
Guang-Cheng Wang, Chia-Hui Chen, Wen Huang, Kuo-Ji Chen, Ming-Hsiang Song, Ta-Pen Guo
{"title":"Gate-driven 3.3V ESD clamp using 1.8V transistors","authors":"Guang-Cheng Wang, Chia-Hui Chen, Wen Huang, Kuo-Ji Chen, Ming-Hsiang Song, Ta-Pen Guo","doi":"10.1109/ICICDT.2011.5783234","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783234","url":null,"abstract":"A new gate driven 3.3V ESD clamp circuit using 1.8V transistor is proposed. This new clamp circuit is suitable for ESD protection of legacy 3.3V I/O interface circuit in SOC chips which use only 1.8V I/O transistors. This clamp along with 3.3V I/O have been demonstrated in 40nm 1.8V process. Life-time test can pass 1000-hours prolonged operation. ESD/Latch-up can pass HBM 3KV, MM 300V, and +/−200mA current triggering and 4.95V (1.5 × VDD) over-voltage test.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132642720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An integrated HDTV predictive pixel compensator for H.264/AVC decoder 用于H.264/AVC解码器的集成HDTV预测像素补偿器
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783228
Ting-Chi Tong, Yun-Nan Chang
{"title":"An integrated HDTV predictive pixel compensator for H.264/AVC decoder","authors":"Ting-Chi Tong, Yun-Nan Chang","doi":"10.1109/ICICDT.2011.5783228","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783228","url":null,"abstract":"In this paper, a highly efficient pixel compensator architecture for the H.264/AVC standard is proposed which can provide both inter and intra prediction functions for luma and chroma components of pixels. By decomposing the algorithms used for both prediction methods into small micro-operation steps, a suitable common arithmetic unit architecture capable for performing these operations has been determined. Next, taking into account the possible reference sample transfer scenario, the overall compensator architecture consists of some buffers and multiple common arithmetic units considering is proposed. Since both arithmetic units and the intermediate data buffer for both inter and intra prediction processes have been shared, our integrated design can achieve more than 31% reduction of gate count compared with the sum of the separate designs. Our design can also lead to more than 37% saving of gate count compared with the previous designs. Our compensator can decode the videos up to HDTV resolution, and be applied for the dedicated H.264 hardware codec for various consumer devices.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124233600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interconnect test for core-based designs with known circuit characteristics and test patterns 具有已知电路特性和测试模式的基于核心设计的互连试验
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783195
T. Yeh, Sying-Jyan Wang, Katherine Shu-Min Li
{"title":"Interconnect test for core-based designs with known circuit characteristics and test patterns","authors":"T. Yeh, Sying-Jyan Wang, Katherine Shu-Min Li","doi":"10.1109/ICICDT.2011.5783195","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783195","url":null,"abstract":"System-level interconnect structures become much more complicated and dominate overall performance in multi-core systems. In order to facilitate interconnect test in board-level and system-on-chip (SoC) designs, IEEE standards 1149.1 and 1500 are developed. Dedicated design-for-testability (DFT) architectures for interconnect consisting of through-silicon via (TSV) in future 3-D stacked ICs have also been investigated. Whenever DFTs in such designs are not available due to limits of design constraints or overall cost consideration, testing those inaccessible interconnects becomes a difficult problem and it is rarely discussed in the literature. In this paper, we propose an interconnect test scheme that exploits circuit characteristics, inherent test resources in design, and test patterns of embedded cores to test interconnect. Since chips are often tested before interconnect, our scheme utilizes those good chips to propagate test patterns and observe responses of interconnect.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131983983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An ultra-low energy capacitive DAC array switching scheme for SAR ADC in biomedical applications 一种用于生物医学领域SAR ADC的超低能量电容式DAC阵列开关方案
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783223
C. Yuan, Y. Y. Lam
{"title":"An ultra-low energy capacitive DAC array switching scheme for SAR ADC in biomedical applications","authors":"C. Yuan, Y. Y. Lam","doi":"10.1109/ICICDT.2011.5783223","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783223","url":null,"abstract":"This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array, the proposed DAC needed only 33% of the total switches. SPICE simulation results show that the average switching energy can be reduced by more than 50%. An 8-bit SAR-ADC using the proposed switch scheme is designed in Global foundries 65nm CMOS process. The power consumption of the capacitive DAC is 160 nW at 1.2V power supply and 100KS/s.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115231875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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