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2011 IEEE International Conference on IC Design & Technology最新文献

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Architectural-level error-tolerant techniques for low supply voltage cache operation 低电压缓存操作的架构级容错技术
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783196
Shih-Lien Lu, Alaa R. Alameldeen, K. Bowman, Zeshan A. Chishti, C. Wilkerson, Wei Wu
{"title":"Architectural-level error-tolerant techniques for low supply voltage cache operation","authors":"Shih-Lien Lu, Alaa R. Alameldeen, K. Bowman, Zeshan A. Chishti, C. Wilkerson, Wei Wu","doi":"10.1109/ICICDT.2011.5783196","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783196","url":null,"abstract":"Supply voltage (VCC) scaling is the most effective technique for reducing the energy consumption of microprocessors. Since VCC scaling increases the impact of parameter variations on circuit performance and functionality, circuits eventually fall out of specification, thus limiting the minimum operating supply voltage (VCCMIN) for the microprocessor. The last-level cache (LLC) often determines VCCMIN. To maximize cache capacity, the LLC memory cell consists of near minimum-sized transistors, which are highly sensitive to process variations. For a tradition LLC, a small fraction of memory cells with large variations limit the VCCMIN for the entire microprocessor. In this paper, error-tolerant techniques dynamically reconfigure the cache to either disable or correct these failing memory cells to enable a lower VCCMIN at the cost of lower cache capacity, thus enhancing the microprocessor energy efficiency. At the high-VCC operating mode, the cache operates at full capacity to satisfy the high-performance target. At the low-VCC operating mode, energy consumption is the primary concern, and the cache is dynamically reconfigured with lower capacity to mitigate the impact of the failing memory cells on reliability. Since the clock frequency significantly reduces for the low-VCC mode as compared to the high-VCC mode, the reduction in cache capacity has a smaller effect on performance. In comparison to a traditional LLC design, simulation results indicate that the error-tolerant cache techniques decrease VCCMIN by 13–28%, corresponding to a 20–42% reduction in energy per instruction. Adding these techniques only incurs a 5–10% performance penalty at the low-VCC operating mode in comparison with a hypothetical idea cache.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123380419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
SRAM bitcell design for low voltage operation in deep submicron technologies 在深亚微米技术中用于低电压操作的SRAM位单元设计
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783219
Younghwi Yang, Jisu Kim, Hyun-Kook Park, Joseph Wang, G. Yeap, Seong-ook Jung
{"title":"SRAM bitcell design for low voltage operation in deep submicron technologies","authors":"Younghwi Yang, Jisu Kim, Hyun-Kook Park, Joseph Wang, G. Yeap, Seong-ook Jung","doi":"10.1109/ICICDT.2011.5783219","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783219","url":null,"abstract":"As technology scales down, an increasing number of transistors can be integrated into a single chip but process variation becomes more serious. SRAM is one of the key components in a SoC and it occupies a large portion of the SoC. Thus, the SRAM bitcell is typically designed using very small transistors for high integration, which limits the minimum operating voltage (VCCmin) of the SoC because of the large threshold voltage (Vth) mismatch between paired transistors caused by small feature size. As process technology scales down to sub-32nm technology, the 6T SRAM bitcell that is currently used may not achieve proper stability, write-ability, and read-ability at the required operating voltage. In this paper, several approaches are investigated to resolve the issue, such as upsized 6T SRAM bitcell, 8T SRAM bitcell, read- and write-preferred bitcells, and read- and write-assist circuits. HSPICE simulations are performed using PTM 32nm model parameters.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128695738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS 40纳米CMOS超低功耗k波段低噪声放大器
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783220
M. Tsai, S. Hsu, F. Hsueh, C. Jou, T. Yeh, Ming-Hsiang Song, J. Tseng
{"title":"An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS","authors":"M. Tsai, S. Hsu, F. Hsueh, C. Jou, T. Yeh, Ming-Hsiang Song, J. Tseng","doi":"10.1109/ICICDT.2011.5783220","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783220","url":null,"abstract":"This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low power UTBOX and back plane (BP) FDSOI technology for 32nm node and below 32nm及以下节点的低功耗UTBOX和背板(BP) FDSOI技术
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783186
C. Fenouillet-Béranger, P. Perreau, L. Tosti, O. Thomas, J. Noel, O. Weber, F. Andrieu, M. Cassé, X. Garros, T. Benoist, S. Haendler, A. Bajolet, F. Bouf, K. Bourdelle, F. Boedt, O. Faynot
{"title":"Low power UTBOX and back plane (BP) FDSOI technology for 32nm node and below","authors":"C. Fenouillet-Béranger, P. Perreau, L. Tosti, O. Thomas, J. Noel, O. Weber, F. Andrieu, M. Cassé, X. Garros, T. Benoist, S. Haendler, A. Bajolet, F. Bouf, K. Bourdelle, F. Boedt, O. Faynot","doi":"10.1109/ICICDT.2011.5783186","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783186","url":null,"abstract":"This paper highlights the interest of FD-SOI with high-k and metal gate as a possible candidate for low power multimedia technology. The possibility of multi-VT by combining UTBOX with back plane, back biasing, variable TiN thickness and Al2O3 in the gate stack is demonstrated. The viability of these approaches is corroborated via mobility and reliability measurements. Dual gate oxide co-integrated devices are reported. The effectiveness of back biasing for short devices is demonstrated through ring oscillators and 0.299µm² SRAM bitcells performance reflecting that the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances are fully compatible with FDSOI. Finally, thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IP's required in a SOC could be demonstrated for LP applications.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125447480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Adaptable stimulus driver for epileptic seizure suppression 抑制癫痫发作的适应性刺激驱动
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783233
M. Ker, Wei-Ling Chen, Chun-Yu Lin
{"title":"Adaptable stimulus driver for epileptic seizure suppression","authors":"M. Ker, Wei-Ling Chen, Chun-Yu Lin","doi":"10.1109/ICICDT.2011.5783233","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783233","url":null,"abstract":"The novel implantable stimulus driver for epileptic seizure suppression with low power design and adaptive loading consideration was proposed in this work. The stimulus driver consisted of the output stage, charge pump system, and adaptor can constantly provide 40-μA output stimulus currents, as the electrode impedance varies within 10∼300 kΩ. The performances of this design have been successfully verified in a silicon chip fabricated by a 0.35-μm 3.3-V/24-V CMOS process. The power consumption of this work was only 1.1∼1.4 mW. The proposed stimulus driver has been integrated into closed-loop epileptic seizure monitoring and controlling system for animal test.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"449 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Temperature dependence of device mismatch and harmonic distortion in nanoscale uniaxial-strained pMOSFETs 纳米单轴应变pmosfet器件失配和谐波畸变的温度依赖性
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783225
J. Kuo, W. P. Chen, P. Su
{"title":"Temperature dependence of device mismatch and harmonic distortion in nanoscale uniaxial-strained pMOSFETs","authors":"J. Kuo, W. P. Chen, P. Su","doi":"10.1109/ICICDT.2011.5783225","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783225","url":null,"abstract":"This paper examines the temperature dependence of mismatching and harmonic distortion properties in nanoscale uniaxial strained pMOSFETs. Our results reveal that the temperature dependence of drain current mismatch as well as harmonics distortion can be modulated by uniaxial strain. In the high gate-voltage overdrive (|Vgst|) linear region, the compressively-strained device shows smaller increment in drain current mismatch than the unstrained counterpart as temperature decreases. In the high |Vgst| saturation region, opposite to the unstrained case, the drain current mismatch of the compressively-strained device decreases with temperature. The underlying mechanism is the larger temperature sensitivity of carrier mobility for the strained device. The larger temperature sensitivity of carrier mobility may also results in larger temperature sensitivity of the harmonic distortion amplitudes. Our study may provide insights for analog circuit design using advanced strained devices.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127809089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Special considerations for 3DIC circuit design and modeling 3DIC电路设计和建模的特殊考虑
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783200
Sally Liu, Y. Peng, F. Hsueh
{"title":"Special considerations for 3DIC circuit design and modeling","authors":"Sally Liu, Y. Peng, F. Hsueh","doi":"10.1109/ICICDT.2011.5783200","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783200","url":null,"abstract":"In this paper, the new elements in 3DIC are examined for enabling optimal 3D products: including 3D interconnect which maybe the limiting factor to achievable speed; 3D chip design strategy (partition and implementation) to achive optimal performance; wireless testing to address the challenges in testing a partial system / chip before stacking and with limited observation points after stacking.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133326256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation 先进CMOS技术中的ESD射频保护及其寄生电容评估
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783184
P. Galy, J. Jimenez, P. Meuris, W. Schoenmaker, O. Dupuis
{"title":"ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation","authors":"P. Galy, J. Jimenez, P. Meuris, W. Schoenmaker, O. Dupuis","doi":"10.1109/ICICDT.2011.5783184","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783184","url":null,"abstract":"Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125202236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Silicon quantum well light-emitting diode 硅量子阱发光二极管
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783240
S. Saito
{"title":"Silicon quantum well light-emitting diode","authors":"S. Saito","doi":"10.1109/ICICDT.2011.5783240","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783240","url":null,"abstract":"Monolithic light source is the only missing component to realize all silicon based photonics for high density and low power optical interconnections. In this paper, we will review our attempts to develop light-emitting devices based on silicon quantum wells made by state-of-the-art silicon process.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129406942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design 瞬态-数字转换器检测电快速瞬态(EFT)扰动，用于系统保护设计
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783183
Cheng-Cheng Yen, Wan-Yen Lin, M. Ker, Ching-Ling Tsai, Shih-Fan Chen, Tung-Yang Chen
{"title":"Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design","authors":"Cheng-Cheng Yen, Wan-Yen Lin, M. Ker, Ching-Ling Tsai, Shih-Fan Chen, Tung-Yang Chen","doi":"10.1109/ICICDT.2011.5783183","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783183","url":null,"abstract":"New on-chip 4-bit transient-to-digital converter for electrical fast transient (EFT) protection design has been proposed. The converter is designed to detect EFT-induced transient disturbances and transfer different EFT voltages into digital codes under EFT tests. The experimental results in silicon chip have confirmed the successful digital output codes.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132338729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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