40纳米CMOS超低功耗k波段低噪声放大器

M. Tsai, S. Hsu, F. Hsueh, C. Jou, T. Yeh, Ming-Hsiang Song, J. Tseng
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引用次数: 4

摘要

提出了一种基于40纳米CMOS技术的k波段低噪声放大器(LNA)与ESD保护电路协同设计。通过将ESD器件作为输入匹配网络的一部分,我们演示了一个ESD保护的24ghz LNA,其NF值为3.2 dB,功耗仅为4.1 mW。该ESD保护网络由双二极管和栅极驱动电源钳组成,实现2.8 kV人体模型(HBM) ESD电平。由于采用协同设计方法,与没有ESD网络的参考LNA相比,NF仅下降0.2 dB。该ESD-LNA的功率增益为13.0 dB,输入和输出回波损耗均大于10 dB。据我们所知,这是关于40纳米CMOS中24 ghz esd保护LNA的第一份报告。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS
This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS.
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