M. Tsai, S. Hsu, F. Hsueh, C. Jou, T. Yeh, Ming-Hsiang Song, J. Tseng
{"title":"An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS","authors":"M. Tsai, S. Hsu, F. Hsueh, C. Jou, T. Yeh, Ming-Hsiang Song, J. Tseng","doi":"10.1109/ICICDT.2011.5783220","DOIUrl":null,"url":null,"abstract":"This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on IC Design & Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2011.5783220","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS.