ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation

P. Galy, J. Jimenez, P. Meuris, W. Schoenmaker, O. Dupuis
{"title":"ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation","authors":"P. Galy, J. Jimenez, P. Meuris, W. Schoenmaker, O. Dupuis","doi":"10.1109/ICICDT.2011.5783184","DOIUrl":null,"url":null,"abstract":"Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on IC Design & Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2011.5783184","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

Abstract

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM.
先进CMOS技术中的ESD射频保护及其寄生电容评估
对于先进的CMOS技术来说,静电放电(ESD)保护是一个挑战,因为缩小了尺寸,降低了固有的稳健性。此外,另一个挑战是模拟IO板中的RF ESD保护。因此,当您合并这两个主题时,挑战是主要的。本文展示了在1kV和2kV HBM下,在C65nm和C45nm下达到10Ghz和20Ghz带宽的ESD RF寄生电容的方法、工具和硅测量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信