先进CMOS技术中的ESD射频保护及其寄生电容评估

2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI:10.1109/ICICDT.2011.5783184

P. Galy, J. Jimenez, P. Meuris, W. Schoenmaker, O. Dupuis

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引用次数: 11

摘要

对于先进的CMOS技术来说，静电放电(ESD)保护是一个挑战，因为缩小了尺寸，降低了固有的稳健性。此外，另一个挑战是模拟IO板中的RF ESD保护。因此，当您合并这两个主题时，挑战是主要的。本文展示了在1kV和2kV HBM下，在C65nm和C45nm下达到10Ghz和20Ghz带宽的ESD RF寄生电容的方法、工具和硅测量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM.

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2011 IEEE International Conference on IC Design & Technology

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