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Enabling TLM-2.0 interface on QEMU and SystemC-based virtual platform 在QEMU和基于systemc的虚拟平台上启用TLM-2.0接口
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783207
Tse-Chen Yeh, Zin-Yuan Lin, Ming-Chao Chiang
{"title":"Enabling TLM-2.0 interface on QEMU and SystemC-based virtual platform","authors":"Tse-Chen Yeh, Zin-Yuan Lin, Ming-Chao Chiang","doi":"10.1109/ICICDT.2011.5783207","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783207","url":null,"abstract":"This paper presents a QEMU and SystemC-based virtual platform that is capable of hardware modeling using TLM-2.0 interface. The proposed virtual platform is not only capable of running an operating system, but it is also capable of using such an interface to connect hardware models, such as the instruction set simulator to a bus model. We verify the functionality of such a platform by using it to boot up a full-fledged Linux while at the same time estimating its performance at the instruction-accurate level. Furthermore, TLM-2.0 interface makes our framework more compatible with other models using TLM-2.0 and more suitable for modeling at the early stage of ESL design flow.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115990198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A frequency-shift readout system for FPW allergy biosensor 一种用于FPW变态反应生物传感器的频移读出系统
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783241
Chia-Hao Hsu, Yain-Reu Lin, Yue-Da Tsai, Yun-Chi Chen, Chua-Chin Wang
{"title":"A frequency-shift readout system for FPW allergy biosensor","authors":"Chia-Hao Hsu, Yain-Reu Lin, Yue-Da Tsai, Yun-Chi Chen, Chua-Chin Wang","doi":"10.1109/ICICDT.2011.5783241","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783241","url":null,"abstract":"In this paper, an IgE antigen concentration measurement system using a frequency-shift readout method for a two-port FPW (flexural plate-wave) allergy biosensor is presented. The proposed frequency-shift readout method adopts a peak detecting scheme to detect the resonant frequency. A linear frequency generator, a pair of peak detectors, two registers, and an subtractor are only needed in our system. According to the specification of the FPW allergy biosensor, the frequency sweep range is limited in 2 MHz to 10 MHz. The sensitivity of the peak detector is 0.8 mV. The proposed frequency-shift readout circuit is verified on silicon by using a standard 0.18 µm CMOS technology. The maximal power consumption is 12.94 mW@0.1 MHz clock given by HSPICE simulations.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124484753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Microwatt low-noise variable-gain amplifier 微瓦低噪声变增益放大器
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783218
Chun-Yi Li, Yu-Bin Lin, R. Rieger
{"title":"Microwatt low-noise variable-gain amplifier","authors":"Chun-Yi Li, Yu-Bin Lin, R. Rieger","doi":"10.1109/ICICDT.2011.5783218","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783218","url":null,"abstract":"A fully integrated variable gain amplifier circuit is reported in this paper. The amplifier is based on an integrating topology allowing the gain to be controlled by the timing of a clock signal. The recording of physiological signals such as the electroneurogram (ENG) or electromyogram (EMG) is a targeted application. Therefore, low-noise performance and low power consumption are important. Simulated and measured results for a chip fabricated in 0.35μm CMOS technology show a gain range from 10–133 V/V, 169 nV/√Hz input spot noise, a NEF of 10.1 and an active area of 0.017 mm2 with a power consumption of 1.44 μW using ±0.9 V supplies.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122275851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-cost embedded Flash memory technology 低成本嵌入式闪存技术
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783211
Wein-Town Sun, Cheng-Jye Liu, C. Lo, Y. Ting, Ying-Je Chen, Tai-Yi Wu, E. Toh, Xiao-Hong Yuan, Ko-Li Low, Qiu Han, Y. You, Y. Leung, S. Woo
{"title":"Low-cost embedded Flash memory technology","authors":"Wein-Town Sun, Cheng-Jye Liu, C. Lo, Y. Ting, Ying-Je Chen, Tai-Yi Wu, E. Toh, Xiao-Hong Yuan, Ko-Li Low, Qiu Han, Y. You, Y. Leung, S. Woo","doi":"10.1109/ICICDT.2011.5783211","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783211","url":null,"abstract":"A simple and low cost logic based single poly Flash memory technology, NeoFlash®, with fast programming and high reliability is demonstrated in this paper. Programming with channel hot-hole-induced hot-electron injection and erasure with uniform channel Fowler-Nordheim tunneling are utilized to achieve fast programming, high endurance and good reliability characteristics. Owing to its simple cell structure and operation schemes, only 3 additional non-critical masks are needed, and the complexity of process integration and device tuning is much reduced. The SONOS based technology has been successfully embedded into 0.35μm ∼ 65nm CMOS logic process. Because of electrons stored in nitride layer of ONO film, no tail bit during endurance and retention test is observed. As a result, NeoFlash® is a promising embedded Flash technology for SoC applications.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132054781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Impact of La on the bias-temperature instability of the HfSiO High-κ n-MOSFET La对HfSiO高κ n-MOSFET偏置温度不稳定性的影响
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783214
D. Ang, G. Du
{"title":"Impact of La on the bias-temperature instability of the HfSiO High-κ n-MOSFET","authors":"D. Ang, G. Du","doi":"10.1109/ICICDT.2011.5783214","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783214","url":null,"abstract":"Lanthanum (La), which has been used in recent works to tune the threshold voltage of HfSiO high-κ n-MOSFETs, is shown to introduce a new bulk degradation mechanism. Unlike the conventional charge trapping mechanism which exhibits low activation energy (∼0.05 eV) and fast post-stress recovery, the La induced degradation mechanism is found to be relatively permanent and has higher activation energy (∼0.26 eV). The latter is expected to have a significant impact on the positive-bias temperature instability of n-MOSFETs employing La-doped high-κ gate dielectrics.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131244100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process 基于65纳米CMOS工艺的MOM电容和STSCR低漏功率轨ESD箝位电路设计
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783185
Po-Yen Chiu, M. Ker
{"title":"Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process","authors":"Po-Yen Chiu, M. Ker","doi":"10.1109/ICICDT.2011.5783185","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783185","url":null,"abstract":"A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 µA under the same bias condition.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133555565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Domestic Indirect Feedback Compensation of multiple-stage amplifiers for multiple-voltage level-converting amplification 国内多级放大器的间接反馈补偿，用于多电压电平转换放大
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783217
Shang-Hsien Yang, Chua-Chin Wang
{"title":"Domestic Indirect Feedback Compensation of multiple-stage amplifiers for multiple-voltage level-converting amplification","authors":"Shang-Hsien Yang, Chua-Chin Wang","doi":"10.1109/ICICDT.2011.5783217","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783217","url":null,"abstract":"This investigation presents a Domestic Indirect Feedback Compensation (DIFC) operational amplifier for systems with both low voltage and high voltage circuits. The DIFC operational amplifier is capable of converting a voltage signal from a low voltage circuit and amplifying it into a large voltage signal to drive high voltage load. Since the Metal-Insulator-Metal (MIM) capacitors are not designed for high voltage applications and the feed-forward compensation causes pole-zero doublet as a result from the deviation of high voltage transistor characteristics from shuttle to shuttle, the DIFC is performed only using low voltage circuits. In other words, the feedback by connecting the output node of the operational amplifier is avoided. The proposed design is carried out using the TSMC 0.25 µm 1-poly 3-metal BCD process.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115377269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Variability analysis of UTB SOI subthreshold SRAM considering Line-Edge Roughness, Work Function Variation and temperature sensitivity 考虑线边缘粗糙度、功函数变化和温度敏感性的UTB SOI亚阈值SRAM变异性分析
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783189
V. Hu, M. Fan, P. Su, C. Chuang
{"title":"Variability analysis of UTB SOI subthreshold SRAM considering Line-Edge Roughness, Work Function Variation and temperature sensitivity","authors":"V. Hu, M. Fan, P. Su, C. Chuang","doi":"10.1109/ICICDT.2011.5783189","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783189","url":null,"abstract":"This paper analyzes stability and variability of Ultra-Thin-Body (UTB) SOI subthreshold SRAMs considering Line-Edge Roughness (LER), Work Function Variation (WFV) and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (μRSNM/σRSNM > 6 at Vdd = 0.3∼0.4V). Higher temperature increases the Vread, 0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs show less temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40nm and 25nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-edge work functions, the Lg = 25nm UTB SOI subthreshold SRAMs show 31.9% reduction in σ RSNM and 55% improvement in μRSNM/σRSNM compared with that using single mid-gap work function.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124133474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impacts of intrinsic device variations on the stability of FinFET subthreshold SRAMs 器件固有变化对FinFET亚阈值sram稳定性的影响
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783210
Yin-Nien Chen, Chien-Yu Hsieh, M. Fan, V. Hu, P. Su, C. Chuang
{"title":"Impacts of intrinsic device variations on the stability of FinFET subthreshold SRAMs","authors":"Yin-Nien Chen, Chien-Yu Hsieh, M. Fan, V. Hu, P. Su, C. Chuang","doi":"10.1109/ICICDT.2011.5783210","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783210","url":null,"abstract":"In this work, we investigate the impacts of intrinsic device variations on FinFET subthreshold SRAMs, including the conventional tied-gate 6T SRAM, tied-gate 10T Schmitt Trigger based SRAMs, and recently proposed independent-gate controlled 8T Schmitt Trigger based SRAMs. The impacts of intrinsic random device variations, including Fin Line-Edge Roughness (LER) and Work Function Variation (WFV), on the device threshold voltage Vth, Subthreshold Swing (S.S.) and stability of FinFET SRAMs operating in subthreshold region are assessed using 3D atomistic mixed-mode Monte-Carlo simulations. The results indicate that Fin LER is the dominant factor limiting the stability of FinFET subthreshold SRAMs, since Fin LER degrades both Vth fluctuation and S.S., while WFV mainly affects only Vth fluctuation. The independent-gate controlled Schmitt Trigger SRAMs are shown to offer adequate stability for the intended subthreshold applications even considering intrinsic device variations.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121179752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
IBM zEnterpriseTM energy efficient 5.2Ghz processor chip IBM zEnterpriseTM节能5.2Ghz处理器芯片
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783229
H. Wen, J. Warnock, Y. Chan, G. Mayer, B. Truong, T. Strach, T. Slegel, S. Carey, G. Salem, F. Malgioglio, D. Malone, D. Plass, B. Curran, Y. Chan, M. Mayo, W. Huott, P. Mak
{"title":"IBM zEnterpriseTM energy efficient 5.2Ghz processor chip","authors":"H. Wen, J. Warnock, Y. Chan, G. Mayer, B. Truong, T. Strach, T. Slegel, S. Carey, G. Salem, F. Malgioglio, D. Malone, D. Plass, B. Curran, Y. Chan, M. Mayo, W. Huott, P. Mak","doi":"10.1109/ICICDT.2011.5783229","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783229","url":null,"abstract":"The IBM zEnterprise z196 processor chip is an energy efficient high-frequency, high-performance design that implements 4 processor cores optimized for maximum single-thread performance. Chip energy efficiency is improved by 25% compared to the previous 65nm design, which enables the processor chip to run at product frequency of 5.2 GHz, providing a significant performance boost for the z196 system. This paper discusses the enablement of a high frequency and high performance design with a focus on energy consumption challenges and solutions. Design tradeoffs for processor speed, performance and energy consumption were optimized during project concept phase and practiced through detailed implementation stages on all aspects of the processor design. Various high speed circuit techniques were deployed to achieve the high frequency goal and improve overall energy efficiency. A comprehensive power methodology was developed to calculate leakage and dynamic power dissipation at various workloads. Sustained thermal power as well as instantaneous peak power was analyzed and worked on throughout the entire design process. The final design stays within the system power constraints and achieves a 5.2Ghz product frequency.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115965100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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