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2011 IEEE International Conference on IC Design & Technology最新文献

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Soft error modeling, simulation, and testing at advanced technology nodes 在高级技术节点上进行软错误建模、仿真和测试
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783237
B. Bhuva, W. T. Holman, L. Massengill
{"title":"Soft error modeling, simulation, and testing at advanced technology nodes","authors":"B. Bhuva, W. T. Holman, L. Massengill","doi":"10.1109/ICICDT.2011.5783237","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783237","url":null,"abstract":"As feature sizes decrease, soft errors are expected to become the dominant failure mechanisms for integrated circuits. This paper discusses the challenges that design and reliability engineers will face with the manufacture and test of ICs at advanced technology nodes.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114174100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the impact of the edge profile of interconnects on the occurrence of passivation cracks of plastic-encapsulated electronic power devices 互连线边缘轮廓对塑料封装电子电力器件钝化裂纹产生的影响
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783216
J. Ackaert, D. Vanderstraeten, B. Vandevelde
{"title":"On the impact of the edge profile of interconnects on the occurrence of passivation cracks of plastic-encapsulated electronic power devices","authors":"J. Ackaert, D. Vanderstraeten, B. Vandevelde","doi":"10.1109/ICICDT.2011.5783216","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783216","url":null,"abstract":"Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic-packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand the failure mechanism and its root cause, already a lot of work has been done in the past. However for the first time the impact of the edge profile of the power metal design on the amount of passivation cracks was investigated in detail. It was found that with a sloped edge profile of the power metal, as it is achieved with a combination of an isotropic wet etch followed by a dry etch, the number of passivation cracks is reduced significantly. The observation is confirmed by a 3-D FEM simulation. The simulation enabled to quantify the stress level and to forecast corresponding levels of cracks observed after temperature cycling. As a result, a robust metal edge profile design could be deduced, which led to a distinct reduction of the principal stress at the most critical positions and, consequently, to a reduction of passivation damage.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125948146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Crystallization technique of epitaxial HfO2 thin films on Si substrates and their potential for advanced high-k gate stack technology Si衬底外延HfO2薄膜的结晶技术及其在先进高k栅极堆叠技术中的潜力
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783212
S. Migita, H. Ota
{"title":"Crystallization technique of epitaxial HfO2 thin films on Si substrates and their potential for advanced high-k gate stack technology","authors":"S. Migita, H. Ota","doi":"10.1109/ICICDT.2011.5783212","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783212","url":null,"abstract":"Crystalline phase high-k films are promising gate stack structure for the advanced CMOS technology because they are thermodynamically stable and have higher dielectric constant when compared with amorphous phase high-k films. A disadvantage of crystalline high-k films, however, is the large leakage current, which is sometimes caused by grain boundaries and non-crystallized region in ultra-thin crystalline high-k films. We developed a unique crystallization technique that realizes epitaxial growth of HfO2 films on Si substrates. MOS capacitors of closely packed epitaxial HfO2 films achieved extremely small EOT with suppressed leakage current. It demonstrates that crystallization process is the key for the application of high-k crystal films.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121913442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Evaluation of DC and AC performance of junctionless MOSFETs in the presence of variability 可变性下无结mosfet的直流和交流性能评估
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783243
Xin Qian, Yinglin Yang, Zhiwei Zhu, Shi-Li Zhang, Dongping Wu
{"title":"Evaluation of DC and AC performance of junctionless MOSFETs in the presence of variability","authors":"Xin Qian, Yinglin Yang, Zhiwei Zhu, Shi-Li Zhang, Dongping Wu","doi":"10.1109/ICICDT.2011.5783243","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783243","url":null,"abstract":"In this paper, DC and AC performance of junctionless MOSFETs are extensively examined. A comparison is made between double-gate junctionless MOSFETs and conventional inversion-mode MOSFETs with an emphasis on the variability in performance. Despite clear benefits by eliminating junctions and related junction variabilities, junctionless MOSFETs are found to require double- or multi-gate in order to be fully turned off. They are also significantly more sensitive to variations of channel thickness and channel doping concentration. Though junctionless MOSFETs demonstrate lower driving current and transconductance, they exhibit significantly lower gate capacitances at saturation region and slower degradation of transconductance over gate overdrive.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122241241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Design of on-chip Transient Voltage Suppressor in a silicon-based transceiver IC to meet IEC system-level ESD specification 满足IEC系统级ESD规范的硅基收发器芯片上瞬态电压抑制器的设计
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783236
Ryan Hsin-Chin Jiang, Tang-Kuei Tseng, Chi-Hao Chen, Che-Hao Chuang
{"title":"Design of on-chip Transient Voltage Suppressor in a silicon-based transceiver IC to meet IEC system-level ESD specification","authors":"Ryan Hsin-Chin Jiang, Tang-Kuei Tseng, Chi-Hao Chen, Che-Hao Chuang","doi":"10.1109/ICICDT.2011.5783236","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783236","url":null,"abstract":"The on-chip Transient Voltage Suppressor (TVS) embedded in the silicon based transceiver IC has been proposed in this paper by using 0.8 μm Bipolar-CMOS-DMOS (BCD) process. The structure of the on-chip TVS is a high voltage Dual Silicon-Controlled-Rectifier (DSCR) with ±19V of high holding voltage (Vh) under the evaluation of 100ns pulse width of the Transmission Line Pulsing (TLP) system. The holding current (Ih) of the on-chip TVS is so high that can pass ±200mA latchup testing. Therefore, the on-chip TVS can be safely applied to protect the ±12V of signal level for RS232. The RS232 transceiver IC with on-chip TVS has been evaluated to pass the IEC61000-4-2 contact ±12kV stress without any hard damages and latchup issue. Moreover, the RS232 transceiver IC also has been verified to well protect the system over the IEC61000-4-2 contact ±20kV stress (CLASS B) in the smart scanner and notebook application","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131067440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fast custom network topology generation with floorplanning for NoC-based systems 一个快速自定义网络拓扑生成与平面规划的基于网络的系统
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783208
Katherine Shu-Min Li, Shu-Yu Chen, Liang-Bi Chen, Ruei-Ting Gu
{"title":"A fast custom network topology generation with floorplanning for NoC-based systems","authors":"Katherine Shu-Min Li, Shu-Yu Chen, Liang-Bi Chen, Ruei-Ting Gu","doi":"10.1109/ICICDT.2011.5783208","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783208","url":null,"abstract":"This paper proposes a fast full-chip synthesis methodology which can be built a custom Network-on-Chip (NoC) topology for NoC-based systems. The processors and their communications are synthesized simultaneously in the system-level floorplanning process. The proposed method leads to accurate area estimation, which makes an algorithm much more efficient than previous approaches. Moreover, the wirelength-aware floorplanning is carried out to optimize circuit size as well as wire length. As a result, experimental results show that the proposed approach produces custom NoCs with better performance than previous methods while the computation time is significantly shorter. This method is also more scalable, which makes it ideal for complicated NoC-based systems.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133102931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparative analysis of flip-flop designs for soft errors at advanced technology nodes 针对先进技术节点软误差的触发器设计对比分析
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783239
B. Bhuva, K. Lilja, J. Holts, S. Wen, R. Wong, S. Jagannathan, T. D. Loveless, M. Mccurdy, Z. Diggins
{"title":"Comparative analysis of flip-flop designs for soft errors at advanced technology nodes","authors":"B. Bhuva, K. Lilja, J. Holts, S. Wen, R. Wong, S. Jagannathan, T. D. Loveless, M. Mccurdy, Z. Diggins","doi":"10.1109/ICICDT.2011.5783239","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783239","url":null,"abstract":"For advanced fabrication technology nodes, novel single-event related failures are being observed. This paper details efforts to use 3D TCAD simulations to model these failure mechanisms and develop mitigation techniques for flip-flop designs. Simulation, as well as experimental, results are used to show validity of such an approach for future CMOS technologies.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116038641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Slew-rate controlled output stages for switching DC-DC converters 用于切换DC-DC转换器的回转速率控制输出级
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783224
Jia-Ming Liu, Yi-Cheng Huang, Yu-Chun Ying, T. Kuo
{"title":"Slew-rate controlled output stages for switching DC-DC converters","authors":"Jia-Ming Liu, Yi-Cheng Huang, Yu-Chun Ying, T. Kuo","doi":"10.1109/ICICDT.2011.5783224","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783224","url":null,"abstract":"Large supply bouncing due to the fast switching current and parasitic inductance of the supply rail may cause reliability and electromagnetic interference (EMI) problems, especially for ICs with the pulse-width modulation (PWM) technique, such as switching DC-DC converters. In this paper, a new slew-rate controlled (SRC) output stage is proposed to appropriately increase the rise and fall times of the PWM output by combining a feedback capacitor technique and a distributed-and-weighted design. Therefore, the supply bouncing during PWM switching can be reduced. The SRC output stage is successfully integrated into a DC-DC converter implemented with a 0.35mm 1P4M 3.3V mixed-signal CMOS process for verification. With an input voltage of 3.3V, an output voltage of 1.8V, a switching frequency of 500 kHz, and a load current range of 700mA, the active area of the converter is 2.3mm2. With a merely 0.035mm2 control circuit for the SRC output stage, the measured supply bouncing of the designed converter can be reduced by 40% and thus the reliability and the EMI can be improved.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116110148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultra-low power FIR filter using STSC-CVL logic 超低功耗FIR滤波器采用STSC-CVL逻辑
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783230
Sajib Roy, Murad Kabir Nipun, J. Wikner
{"title":"Ultra-low power FIR filter using STSC-CVL logic","authors":"Sajib Roy, Murad Kabir Nipun, J. Wikner","doi":"10.1109/ICICDT.2011.5783230","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783230","url":null,"abstract":"The paper shows the implementation of digital FIR filter using ultra-low power logic components. Source coupled logic is used and operated at sub-threshold region to achieve low power consumption while keeping a satisfactory output swing. The STSCL (sub-threshold source coupled logic) circuit is added with controllable voltage-level feature to minimize overall leakage current flow, including both gate leakage and sub-threshold. Seven-stage ring oscillators are implemented in CMOS, STSCL and our proposed logic at similar supply voltage to observe the differences with power consumption for the proposed technique came at nW range. Later on the FIR was design in both CMOS and proposed with measurement results shown in the paper. All measurements for are shown using 65 nm process technology, at a supply voltage of 0.5 V.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI 超薄SOI上优异的硅厚均匀性控制FDSOI的Vt变化
2011 IEEE International Conference on IC Design & Technology Pub Date : 2011-05-02 DOI: 10.1109/ICICDT.2011.5783188
W. Schwarzenbach, X. Cauchy, F. Boedt, O. Bonnin, E. Butaud, C. Girard, B. Nguyen, C. Mazure, C. Maleville
{"title":"Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI","authors":"W. Schwarzenbach, X. Cauchy, F. Boedt, O. Bonnin, E. Butaud, C. Girard, B. Nguyen, C. Mazure, C. Maleville","doi":"10.1109/ICICDT.2011.5783188","DOIUrl":"https://doi.org/10.1109/ICICDT.2011.5783188","url":null,"abstract":"Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCutTM technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121097862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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