A fast custom network topology generation with floorplanning for NoC-based systems

Abstract

This paper proposes a fast full-chip synthesis methodology which can be built a custom Network-on-Chip (NoC) topology for NoC-based systems. The processors and their communications are synthesized simultaneously in the system-level floorplanning process. The proposed method leads to accurate area estimation, which makes an algorithm much more efficient than previous approaches. Moreover, the wirelength-aware floorplanning is carried out to optimize circuit size as well as wire length. As a result, experimental results show that the proposed approach produces custom NoCs with better performance than previous methods while the computation time is significantly shorter. This method is also more scalable, which makes it ideal for complicated NoC-based systems.