On the impact of the edge profile of interconnects on the occurrence of passivation cracks of plastic-encapsulated electronic power devices

Abstract

Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic-packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand the failure mechanism and its root cause, already a lot of work has been done in the past. However for the first time the impact of the edge profile of the power metal design on the amount of passivation cracks was investigated in detail. It was found that with a sloped edge profile of the power metal, as it is achieved with a combination of an isotropic wet etch followed by a dry etch, the number of passivation cracks is reduced significantly. The observation is confirmed by a 3-D FEM simulation. The simulation enabled to quantify the stress level and to forecast corresponding levels of cracks observed after temperature cycling. As a result, a robust metal edge profile design could be deduced, which led to a distinct reduction of the principal stress at the most critical positions and, consequently, to a reduction of passivation damage.