B. Bhuva, K. Lilja, J. Holts, S. Wen, R. Wong, S. Jagannathan, T. D. Loveless, M. Mccurdy, Z. Diggins
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Comparative analysis of flip-flop designs for soft errors at advanced technology nodes
For advanced fabrication technology nodes, novel single-event related failures are being observed. This paper details efforts to use 3D TCAD simulations to model these failure mechanisms and develop mitigation techniques for flip-flop designs. Simulation, as well as experimental, results are used to show validity of such an approach for future CMOS technologies.