Interconnect test for core-based designs with known circuit characteristics and test patterns

Abstract

System-level interconnect structures become much more complicated and dominate overall performance in multi-core systems. In order to facilitate interconnect test in board-level and system-on-chip (SoC) designs, IEEE standards 1149.1 and 1500 are developed. Dedicated design-for-testability (DFT) architectures for interconnect consisting of through-silicon via (TSV) in future 3-D stacked ICs have also been investigated. Whenever DFTs in such designs are not available due to limits of design constraints or overall cost consideration, testing those inaccessible interconnects becomes a difficult problem and it is rarely discussed in the literature. In this paper, we propose an interconnect test scheme that exploits circuit characteristics, inherent test resources in design, and test patterns of embedded cores to test interconnect. Since chips are often tested before interconnect, our scheme utilizes those good chips to propagate test patterns and observe responses of interconnect.