{"title":"使用备选路径最小化TSV数量","authors":"Chun-Hua Cheng, Chih-Hsien Kuo, Shih-Hsu Huang","doi":"10.1109/ICICDT.2011.5783203","DOIUrl":null,"url":null,"abstract":"In a three-dimensional integrated circuit (3D IC) design, through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic for 3D IC design. In this paper, we point out that there often exist idle functional units and idle TSVs at each control step. If we use idle functional units and idle TSVs to form an alternative path to replace direct TSVs for data transfer, the number of TSVs can be reduced. Based on that observation, we present an ILP (integer linear programming) approach to formally draw up our problem. Given a high-level synthesis result and a clock period constraint, we perform post-processing to fully utilize alternative paths for TSV number minimization. Compared with previous work that minimizes the TSV number without considering alternative paths, experimental results show that our approach can further reduce 16.92% TSV number without affecting the circuit performances.","PeriodicalId":402000,"journal":{"name":"2011 IEEE International Conference on IC Design & Technology","volume":"01 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"TSV number minimization using alternative paths\",\"authors\":\"Chun-Hua Cheng, Chih-Hsien Kuo, Shih-Hsu Huang\",\"doi\":\"10.1109/ICICDT.2011.5783203\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In a three-dimensional integrated circuit (3D IC) design, through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic for 3D IC design. In this paper, we point out that there often exist idle functional units and idle TSVs at each control step. If we use idle functional units and idle TSVs to form an alternative path to replace direct TSVs for data transfer, the number of TSVs can be reduced. Based on that observation, we present an ILP (integer linear programming) approach to formally draw up our problem. Given a high-level synthesis result and a clock period constraint, we perform post-processing to fully utilize alternative paths for TSV number minimization. Compared with previous work that minimizes the TSV number without considering alternative paths, experimental results show that our approach can further reduce 16.92% TSV number without affecting the circuit performances.\",\"PeriodicalId\":402000,\"journal\":{\"name\":\"2011 IEEE International Conference on IC Design & Technology\",\"volume\":\"01 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-05-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference on IC Design & Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2011.5783203\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on IC Design & Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2011.5783203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In a three-dimensional integrated circuit (3D IC) design, through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic for 3D IC design. In this paper, we point out that there often exist idle functional units and idle TSVs at each control step. If we use idle functional units and idle TSVs to form an alternative path to replace direct TSVs for data transfer, the number of TSVs can be reduced. Based on that observation, we present an ILP (integer linear programming) approach to formally draw up our problem. Given a high-level synthesis result and a clock period constraint, we perform post-processing to fully utilize alternative paths for TSV number minimization. Compared with previous work that minimizes the TSV number without considering alternative paths, experimental results show that our approach can further reduce 16.92% TSV number without affecting the circuit performances.