Beta-Matrix ESD network: Throughout end of placement rules?

Abstract

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is based on efficient device Network. But these protection strategies imply some constraint on IO and particularly on the frame and the placement in IO ring. In this context we develop and propose an ESD network with Beta-Matrix power device and its own trigger circuit which are integrated in each IO. We obtain a new local strategy which allows removing all IO placement constraint.