Timing error prevention using elastic clocking

Abstract

“Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking. Time borrowing allows a pipeline to compensate the timing slack by borrowing time from the next pipeline stage and clock stretching pays back the borrowed time to the next pipeline stage. Thus, a system employing such dynamic timing control technique can prevent errors with a small performance penalty and eventually operate without safety margin. The net effect is better power-performance trade-off under voltage scaling i.e. lower power consumption for a target frequency or higher operating frequency for a target power. The proposed technique was validated using a prototype test-chip designed in 180-nm CMOS technology.