A 8-bit 50-Msamples/s switched-current pipelined ADC with residue generator and interlaced stage

This paper presents a 8-bit 50-MHz sampling rate switched-current pipelined analog-to-digital converter (ADC) in a standard 0.35-μm 2P4M CMOS process. Not only a new residue generator is proposed to cancel the sub-DAC circuit, but also an interlaced arrangement is adopted to improve the transmission error in a seven-stage pipelined ADC. That is, the odd stage adopts the traditional structure and the even stage employs the proposed residue generator. The simulated results reveal that power dissipation is 160mW and sampling rate is 50 MHz at a supply voltage of 3.3 V. As a sinusoidal waveform with 1 MHz sampling rate is adopted, a signal to noise distortion ratio (SNDR) of 48 dB and an effective number of bits (ENOB) of 7.7 bits are demonstrated. Additionally, the differential nonlinearity (DNL) of −0.4 LSB ∼ +0.3 LSB and the integral nonlinearity (INL) of −0.7 LSB ∼ +0.8 LSB are presented with a chip area of roughly 1.59 × 1.63 mm2.