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2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)最新文献

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Signal slope modulation method for high data transfer rates and reducing wiring density in high-speed digital systems 高速数字系统中用于高数据传输速率和降低布线密度的信号斜率调制方法
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329700
M. Bohra, Jinwoo Choi, Yanyan Zhang, L. Walls
{"title":"Signal slope modulation method for high data transfer rates and reducing wiring density in high-speed digital systems","authors":"M. Bohra, Jinwoo Choi, Yanyan Zhang, L. Walls","doi":"10.1109/EPEPS.2017.8329700","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329700","url":null,"abstract":"This paper presents a novel method of transferring data using a signal slope modulation method in high-speed digital systems. For the first time, this paper demonstrates that this signal slope modulation technique can be used for transferring high data per trace as well as for reducing wiring density in packages significantly. The unique combination of serial bus and parallel bus attributes of this method allows higher bit transfer rates, lower clock speeds, and lower trace and wiring counts.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115259169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cost function impact on S-parameter optimization space 代价函数对s参数优化空间的影响
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329742
D. de Araujo, J. Pingenot
{"title":"Cost function impact on S-parameter optimization space","authors":"D. de Araujo, J. Pingenot","doi":"10.1109/EPEPS.2017.8329742","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329742","url":null,"abstract":"Optimization algorithms require a cost function in order to quantitatively compare results and reach convergence to the maxima/minima desired. The choice of cost function can significantly affect the complexity of the optimization space. This work investigates the impact of cost function of S-parameters on the optimization solution space.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124864035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of time delay skew on differential insertion loss in weak and strong coupled PCB traces 弱耦合和强耦合PCB走线中延时倾斜对差分插入损耗的影响
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329757
D. Nozadze, Amendra Koul, Kartheek Nalla, Mike Sapozhnikov, V. Khilkevich
{"title":"Effect of time delay skew on differential insertion loss in weak and strong coupled PCB traces","authors":"D. Nozadze, Amendra Koul, Kartheek Nalla, Mike Sapozhnikov, V. Khilkevich","doi":"10.1109/EPEPS.2017.8329757","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329757","url":null,"abstract":"In this paper, effect of time delay skew (TDS) on differential insertion loss (IL) is studied in both weak and strong forward coupling cases. It is showed that TDS impacts differential IL and impact depends on amount of forward coupling. To predict additional differential IL due to TDS, analytical formula is derived and heuristic formula is constructed based on fitting to simulation results in weak and strong forward coupling cases, respectively. The predictions are validated by simulations and measurements.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reduced pin command and address bus for LPDDR4x using equalization technique 使用均衡技术减少了LPDDR4x的引脚命令和地址总线
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329758
Jun Liao, K. Ganguly, R. Meltser, Jennifer Duong, Stephen P Christianson, X. Cai
{"title":"Reduced pin command and address bus for LPDDR4x using equalization technique","authors":"Jun Liao, K. Ganguly, R. Meltser, Jennifer Duong, Stephen P Christianson, X. Cai","doi":"10.1109/EPEPS.2017.8329758","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329758","url":null,"abstract":"As the number of memory channels keeps increasing for Mobile system, IO pin count is becoming a limiting factor for silicon/package cost scaling and compact platform enabling. The pin count tension is mainly because each channel requires a unique set Command/Address (C/A) pins at DRAM side. In this paper, we discuss the approaches to reduce number of C/A pins for SOC. T topology on motherboard is implemented to group different DRAMs. C/A transmitter equalization is implemented for the first time to enable the double loaded configuration. This solution saves 24 C/A pins on SOC silicon and package while still maintaining the same operation frequency.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121398505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Per-bit equalization approach for multi-level signal in high-speed design 高速设计中多级信号的每比特均衡方法
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329748
J. He, H. Deng, N. Dikhaminjia, M. Tsiklauri, J. Drewniak, A. Chada, B. Mutnury
{"title":"Per-bit equalization approach for multi-level signal in high-speed design","authors":"J. He, H. Deng, N. Dikhaminjia, M. Tsiklauri, J. Drewniak, A. Chada, B. Mutnury","doi":"10.1109/EPEPS.2017.8329748","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329748","url":null,"abstract":"A new feed forward equalization (FFE) method for four-level pulse-amplitude modulation signal (PAM4) is introduced. The new FFE method equalizes the signal by bit instead of by symbol which provide the better high frequency compensation in some situations. The advantages and limitations of per bit FFE is discussed and compared against per symbol FFE. Several test cases are presented to show the advantages and limitations of the new FFE method.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130723018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Using deep neural networks to model nonlinear circuit blocks in wireline links 利用深度神经网络对有线链路中的非线性电路块进行建模
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329721
Arash Zargaran-Yazd, Sunil R. Sudhakaran
{"title":"Using deep neural networks to model nonlinear circuit blocks in wireline links","authors":"Arash Zargaran-Yazd, Sunil R. Sudhakaran","doi":"10.1109/EPEPS.2017.8329721","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329721","url":null,"abstract":"This work presents an approach to model nonlinear circuit blocks, commonly found in serial and memory links, using deep neural networks. Specifically, we discuss modeling and simulation of a variant of analog amplifier, namely continuous-time linear equalize (CTLE). Conventional modeling approaches such as Volterra-series and polynomial-fitting fall short of achieving the desired error compared to Spice-like simulation results which are considered the gold standard. Deep neural networks are theoretically capable of learning and estimating the performance of behaviorally complex systems. As demonstrated in this work, such interconnected grid of nodes can model the behavior of nonlinear analog circuits with residual errors that are much smaller than those of conventional approaches.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132903274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Substrate integrated common mode choke of EMI filter for high speed serial link 用于高速串行链路的 EMI 滤波器基底集成共模扼流圈
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329747
B. Wu
{"title":"Substrate integrated common mode choke of EMI filter for high speed serial link","authors":"B. Wu","doi":"10.1109/EPEPS.2017.8329747","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329747","url":null,"abstract":"A miniaturized substrate integrated common mode chock of EMI filter is presented for high speed serial link. This novel design is implemented on a high density interconnect board. The small size of the component makes it well suitable for system integration and assembly in a highly compact situation. The common mode noise is significantly mitigated according to the post-fabrication spectrum analyses. Good agreement between simulation and measurement is reached and observed.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133353291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-speed channel modeling with deep neural network for signal integrity analysis 基于深度神经网络的高速信道建模与信号完整性分析
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329733
Tianjian Lu, Ken Wu, Zhiping Yang, Ju Sun
{"title":"High-speed channel modeling with deep neural network for signal integrity analysis","authors":"Tianjian Lu, Ken Wu, Zhiping Yang, Ju Sun","doi":"10.1109/EPEPS.2017.8329733","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329733","url":null,"abstract":"In this work, deep neural networks (DNNs) are trained and used to model high-speed channels for signal integrity analysis. The DNN models predict eye-diagram metrics by taking advantage of the large amount of simulation results made available in a previous design or at an earlier design stage. The proposed DNN models characterize high-speed channels through extrapolation with saved coefficients, which requires no complex simulations and can be achieved in a highly efficient manner. It is demonstrated through numerical examples that the proposed DNN models achieve good accuracy in predicting eye-diagram metrics from input design parameters. In the DNN models, no assumptions are made on the distributions of and the interactions among individual design parameters.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133040631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A super broadband DGS-based common-mode filter with a compact dimension 一种尺寸紧凑的超宽带dgs共模滤波器
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329712
Po-Jui Li, Tzong-Lin Wu
{"title":"A super broadband DGS-based common-mode filter with a compact dimension","authors":"Po-Jui Li, Tzong-Lin Wu","doi":"10.1109/EPEPS.2017.8329712","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329712","url":null,"abstract":"This paper proposes a compact DGS-based common-mode filter (CMF) that can provide a ultra large −10 dB-suppression band started from 1.15 GHz, and its equivalent model is built and analyzed. By designing the circuit parameters, six transmission zeros for common mode (CM) can be obtained. The proposed CMF is designed and implemented on a four-layer PCB, and its performance is measured and compared with the simulated results.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124120625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sensitivity of NRZ and PAM4 signaling schemes to channel insertion loss deviation NRZ和PAM4信令方案对信道插入损耗偏差的敏感性
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329746
Giorgi Maghlakelidze, Santhosh Ranga Chavalla, N. Dikhaminjia, J. Drewniak
{"title":"Sensitivity of NRZ and PAM4 signaling schemes to channel insertion loss deviation","authors":"Giorgi Maghlakelidze, Santhosh Ranga Chavalla, N. Dikhaminjia, J. Drewniak","doi":"10.1109/EPEPS.2017.8329746","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329746","url":null,"abstract":"Paper discusses channel Insertion Loss Deviation (ILD) effects on binary and multi-level signaling in high-speed link design. Overview of ILD phenomenon is given and its sources in a multi-stage transmission line are discussed. Comparison tests are provided for channels with different amount of ILD. The test channels were simulated to mimic backplane channels with daughter cards. In order to cause significant ILD, impedance mismatches and interconnect parasitic effects were introduced into the model. Results are analyzed in terms of eye diagram degradations due to ILD induced ISI noise.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125789302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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