Using deep neural networks to model nonlinear circuit blocks in wireline links

Abstract

This work presents an approach to model nonlinear circuit blocks, commonly found in serial and memory links, using deep neural networks. Specifically, we discuss modeling and simulation of a variant of analog amplifier, namely continuous-time linear equalize (CTLE). Conventional modeling approaches such as Volterra-series and polynomial-fitting fall short of achieving the desired error compared to Spice-like simulation results which are considered the gold standard. Deep neural networks are theoretically capable of learning and estimating the performance of behaviorally complex systems. As demonstrated in this work, such interconnected grid of nodes can model the behavior of nonlinear analog circuits with residual errors that are much smaller than those of conventional approaches.