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2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)最新文献

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A novel use of deep learning to optimize solution space exploration for signal integrity analysis 一种新颖的使用深度学习来优化信号完整性分析的解空间探索
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329701
Mruganka Kashyap, Kumar Keshavan, A. Varma
{"title":"A novel use of deep learning to optimize solution space exploration for signal integrity analysis","authors":"Mruganka Kashyap, Kumar Keshavan, A. Varma","doi":"10.1109/EPEPS.2017.8329701","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329701","url":null,"abstract":"The enhanced complexity of electrical devices has increased the number of variables that directly or indirectly affect the output. Consequently, it has become imperative to explore the massive solution space during integrity analyses, without sacrificing accuracy and development time. In this paper, we offer a simple hybrid algorithm based on a Multi-Layer Perceptron that significantly works better than traditional methods like Least Squares, by balancing the requirements for high accuracy and less development time.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"695 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132745630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Signal via coupling effects caused by partially broken high frequency signal return 信号经耦合效应导致高频信号部分破碎返回
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329737
T. Winkel
{"title":"Signal via coupling effects caused by partially broken high frequency signal return","authors":"T. Winkel","doi":"10.1109/EPEPS.2017.8329737","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329737","url":null,"abstract":"Chip package to chip package differential signal line measurements were performed to investigate increased via coupling effects. In via fields, the high frequency signal return was spread over different combinations of power and GND vias. Results are discussed for different experiments.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121322861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A simple method to improve signal integrity of electrostatic discharge protection devices 一种提高静电放电保护装置信号完整性的简单方法
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329739
Yang-Chih Huang, C. Lin, Tzong-Lin Wu
{"title":"A simple method to improve signal integrity of electrostatic discharge protection devices","authors":"Yang-Chih Huang, C. Lin, Tzong-Lin Wu","doi":"10.1109/EPEPS.2017.8329739","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329739","url":null,"abstract":"In this paper, we propose a simple method to compensate the non-ideality of electro-static discharge (ESD) devices on signal integrity (SI). Such method can release the high requirement of small parasitic capacitance of ESD devices. Only two open stubs are required for each trace and the lengths are usually similar to the ESD protection device footprint size. Therefore, this method is cost-effective in real application. To validate the effect of this method, experiments are implemented on a commercial ESD product using for conventional USB 3.0 channel (5Gbps), and the improvement is significant. The results show the eye height is improved by 68 % and the jitter is improved by 44 % for 15Gbps eye diagram test. Therefore, this method has the potential to extend the usable frequency band for ESD protection devices.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122790627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Embeded filtering in PCB integrated ultra high speed dielectric waveguides using photonic band gap structures 利用光子带隙结构在PCB集成超高速介质波导中嵌入滤波
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329753
J. Myers, J. Hejase, Junyan Tang, D. Dreps
{"title":"Embeded filtering in PCB integrated ultra high speed dielectric waveguides using photonic band gap structures","authors":"J. Myers, J. Hejase, Junyan Tang, D. Dreps","doi":"10.1109/EPEPS.2017.8329753","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329753","url":null,"abstract":"Printed circuit board high speed dielectric waveguides operating at frequencies up to 130 GHz with embedded photonic band gap filtering structures are studied. The filters are made of alternating dielectric materials placed within the core of the dielectric waveguide, surrounded by the dielectric waveguide cladding. Properties of the filter such as the number of dielectric transitions and material properties are varied in order to study their effect on the performance of the filter. Single and multi-band filtering within a single waveguide is also examined. Finally, an example application of the embedded filters is shown in a multi-waveguide system to isolate crosstalk between the waveguides in specific frequency bands.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129107773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Output impedance design of distributed domains with high frequency voltage regulators 高频稳压器分布域的输出阻抗设计
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329762
A. Jain, C. Kuan, Sameer Shekhar
{"title":"Output impedance design of distributed domains with high frequency voltage regulators","authors":"A. Jain, C. Kuan, Sameer Shekhar","doi":"10.1109/EPEPS.2017.8329762","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329762","url":null,"abstract":"This paper presents analysis & methodology for impedance design of distributed voltage domains supplied from high frequency voltage regulators (VRs). The approach addresses entire system including the combination of routing parasitics, decoupling capacitor dynamics, and control design for a low impedance solution. The detailed modeling is applicable to any power converter — on die, on package, power management IC (PMIC) & mother board VRs, where control bandwidth, decoupling capacitor & power delivery network (PDN) resonances, and load transients are in a narrow frequency range.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132295344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mixed epistemic-aleatory uncertainty quantification using reduced dimensional polynomial chaos and parametric ANOVA 使用降维多项式混沌和参数方差分析的混合认知-认知不确定性量化
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329716
A. Prasad, Sourajeet Roy
{"title":"Mixed epistemic-aleatory uncertainty quantification using reduced dimensional polynomial chaos and parametric ANOVA","authors":"A. Prasad, Sourajeet Roy","doi":"10.1109/EPEPS.2017.8329716","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329716","url":null,"abstract":"In this paper, a reduced dimensional PC approach is presented to model the impact of both aleatory (random) and epistemic (ignorance based) uncertainty on the response of distributed transmission line networks. The key feature of this approach is the development of a parameterized analysis of variance (PANOVA) strategy to identify which of the aleatory dimensions have minimal impact on the response of the network over the entire multidimensional support of the epistemic dimensions. By removing these statistically insignificant dimensions, a highly compact PC representation of the response can be developed to capture the mixed epistemic-aleatory effects.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120954433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Interpolating inductance coupling effects for package and PCB simulation 封装和PCB仿真中的电感耦合插值效应
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329744
Xin Xu, W. Thiel, J. Bracken
{"title":"Interpolating inductance coupling effects for package and PCB simulation","authors":"Xin Xu, W. Thiel, J. Bracken","doi":"10.1109/EPEPS.2017.8329744","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329744","url":null,"abstract":"A simple interpolating formula is proposed to model the frequency dependent inductance coupling effect between parallel plate and stripline modes. It requires only DC and high-frequency results of a transmission line. These results can be obtained more efficiently as compared to a general wide band 2D full wave simulation algorithm such as FEM or MOM. Numerical tests show that the proposed method agrees reasonably well with 2D full wave simulation","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123372554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accurate and efficient impedance matching method in the presence of on-board and SMT parasitic components 在存在板载和SMT寄生元件的情况下，精确高效的阻抗匹配方法
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329709
Tao Wang, T. Michalka, Gerardo Romo Luevano
{"title":"Accurate and efficient impedance matching method in the presence of on-board and SMT parasitic components","authors":"Tao Wang, T. Michalka, Gerardo Romo Luevano","doi":"10.1109/EPEPS.2017.8329709","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329709","url":null,"abstract":"An accurate and efficient impedance matching methodology for RF channels is presented in this paper. The methodology ensures a feasible impedance matching network and optimal RF channel performance by accounting for the parasitics of discrete SMT components as well as for those of the PCB. Such parasitics need to be included in the full channel simulation because they detune the impedance matching network and can affect the insertion and return loss dramatically. After the entire RF channel is accurately modeled and impedance matched, a bill of material (BOM) file is automatically generated to drive assembly of PCBs based on an integrated EM-schematic co-simulation. An RF channel test bench was built and measured showing good correlation between simulation and measurement, thus validating the proposed methodology.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125690950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Via optimization for next generation speeds 通过优化下一代的速度
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329730
Siang Chen, C. Chen, Chun-Lin Liao, James Chen, Tzong-Lin Wu, B. Mutnury
{"title":"Via optimization for next generation speeds","authors":"Siang Chen, C. Chen, Chun-Lin Liao, James Chen, Tzong-Lin Wu, B. Mutnury","doi":"10.1109/EPEPS.2017.8329730","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329730","url":null,"abstract":"Optimizing via placement is becoming important as signaling speeds increase for next generation interconnects. Random placement of ground (GND) return path vias next to signal vias would result in less than optimal performance of an interconnect. It will result in resonances in insertion loss at higher frequencies. In this paper, a methodology for optimal placement of GND vias is proposed that will not only decrease the resonances in insertion loss but also minimize the crosstalk between adjacent differential vias.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128825231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Signal slope modulation method for high data transfer rates and reducing wiring density in high-speed digital systems 高速数字系统中用于高数据传输速率和降低布线密度的信号斜率调制方法
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 1900-01-01 DOI: 10.1109/epeps.2017.8329723
M. Bohra, Jinwoo Choi, Yanyan Zhang, L. Walls
{"title":"Signal slope modulation method for high data transfer rates and reducing wiring density in high-speed digital systems","authors":"M. Bohra, Jinwoo Choi, Yanyan Zhang, L. Walls","doi":"10.1109/epeps.2017.8329723","DOIUrl":"https://doi.org/10.1109/epeps.2017.8329723","url":null,"abstract":"This paper presents a novel method of transferring data using a signal slope modulation method in high-speed digital systems. For the first time, this paper demonstrates that this signal slope modulation technique can be used for transferring high data per trace as well as for reducing wiring density in packages significantly. The unique combination of serial bus and parallel bus attributes of this method allows higher bit transfer rates, lower clock speeds, and lower trace and wiring counts.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130927647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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