弱耦合和强耦合PCB走线中延时倾斜对差分插入损耗的影响

2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI:10.1109/EPEPS.2017.8329757

D. Nozadze, Amendra Koul, Kartheek Nalla, Mike Sapozhnikov, V. Khilkevich

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引用次数: 1

摘要

在弱前向耦合和强前向耦合两种情况下，研究了时延偏差对差分插入损耗(IL)的影响。结果表明，TDS对差分IL的影响取决于前向耦合的大小。为了预测由于TDS引起的额外差分IL，分别在弱前耦合和强前耦合情况下推导了解析公式，并在拟合模拟结果的基础上构建了启发式公式。通过模拟和测量验证了预测结果。

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Effect of time delay skew on differential insertion loss in weak and strong coupled PCB traces

In this paper, effect of time delay skew (TDS) on differential insertion loss (IL) is studied in both weak and strong forward coupling cases. It is showed that TDS impacts differential IL and impact depends on amount of forward coupling. To predict additional differential IL due to TDS, analytical formula is derived and heuristic formula is constructed based on fitting to simulation results in weak and strong forward coupling cases, respectively. The predictions are validated by simulations and measurements.

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来源期刊

2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

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