Reduced pin command and address bus for LPDDR4x using equalization technique

Abstract

As the number of memory channels keeps increasing for Mobile system, IO pin count is becoming a limiting factor for silicon/package cost scaling and compact platform enabling. The pin count tension is mainly because each channel requires a unique set Command/Address (C/A) pins at DRAM side. In this paper, we discuss the approaches to reduce number of C/A pins for SOC. T topology on motherboard is implemented to group different DRAMs. C/A transmitter equalization is implemented for the first time to enable the double loaded configuration. This solution saves 24 C/A pins on SOC silicon and package while still maintaining the same operation frequency.