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Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting最新文献

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A subnanosecond 64 Kb BiCMOS SRAM 亚纳秒64 Kb BiCMOS SRAM
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587869
M. Santoro, L. Tavrow, G. Bewick
{"title":"A subnanosecond 64 Kb BiCMOS SRAM","authors":"M. Santoro, L. Tavrow, G. Bewick","doi":"10.1109/BIPOL.1994.587869","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587869","url":null,"abstract":"This paper describes a 2K/spl times/32 BiCMOS embedded SRAM which has an access time of 900 ps. The SRAM uses a standard 6T cell combined with an Embedded Access Tree for improved read and write speeds. The SRAM size is comparable to a conventional CMOS design.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131178565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of current and voltage stress on the DC characteristics of SiGe-base heterojunction bipolar transistors 电流和电压应力对硅基异质结双极晶体管直流特性的影响
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587896
K. Liao, R. Reif, T. Kamins
{"title":"Effect of current and voltage stress on the DC characteristics of SiGe-base heterojunction bipolar transistors","authors":"K. Liao, R. Reif, T. Kamins","doi":"10.1109/BIPOL.1994.587896","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587896","url":null,"abstract":"Degradation of SiGe-base HBTs under high-forward-current and reverse-bias stresses are investigated. The observations are explained using existing homojunction theories. Inclusion of Ge into the base may potentially improve the junction reliability of bipolar transistors.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123302194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Voltage scalable GHz interface circuits for BiCMOS applications 用于BiCMOS应用的电压可扩展GHz接口电路
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587870
H. Chang, K. Fung, M. Izzard, D. Scott
{"title":"Voltage scalable GHz interface circuits for BiCMOS applications","authors":"H. Chang, K. Fung, M. Izzard, D. Scott","doi":"10.1109/BIPOL.1994.587870","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587870","url":null,"abstract":"As technology scales, the operating voltage of IC's will drop and chips on a common board may operate at different power supplies. In such a scenario, it becomes necessary for the high speed interface circuits to be not only compatible with a 3.3 V supply, but also with I/O levels of future chips that operate at even lower voltage supplies. This paper examines basic building blocks in communication designs operating at data rates above 2.5 Gbit/s. Our experimental results show that BiCMOS as a technology can be used to implement circuits operating at 2.5 V and below.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116041034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power, high-speed, voltage-feedback operational amplifier on a low-cost 40 volt complementary bipolar technology 基于低成本40伏互补双极技术的低功率、高速、电压反馈运算放大器
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587845
F. Moraveji
{"title":"A low-power, high-speed, voltage-feedback operational amplifier on a low-cost 40 volt complementary bipolar technology","authors":"F. Moraveji","doi":"10.1109/BIPOL.1994.587845","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587845","url":null,"abstract":"A high-speed, low-power voltage-feedback operational amplifier on a low-cost 40 volt complementary bipolar technology is described. The low-current version of this chip has a quiescent current of 2.5 mA at +/-15 V supply voltage, bandwidth of 110 MHz and slew rate of 2000 V/us. The medium-current version draws 6.5 mA of current at the same supply voltage while the bandwidth increases to 200 MHz and higher slewing characteristics. Both parts are operational from +/-3.75 V to +/-18 V supply range. Die size is 51 mils by 76 mils on a poly-emitter CB process.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"67 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131138877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A single-poly BiCMOS technology with 30 GHz bipolar f/sub T/ 30 GHz双极f/sub / T/单聚BiCMOS技术
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587902
C. Wang, J. Van Der Velden
{"title":"A single-poly BiCMOS technology with 30 GHz bipolar f/sub T/","authors":"C. Wang, J. Van Der Velden","doi":"10.1109/BIPOL.1994.587902","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587902","url":null,"abstract":"We present process design and device performance of bipolar transistors embedded in a single-poly BiCMOS technology. The bipolar device possesses a CMOS-like morphology and is easily integrated into a CMOS-based process flow with two additional masks. The integrated process yields a structure with minimum topography. Process concerns associated with the conventional double-poly structure are therefore avoided. Shallow emitter and base junction depth are achieved through a conventional ion implantation approach with proper control of the thermal budget. Bipolar transistors featuring 31 GHz bipolar f/sub T/ and 4 V BV/sub ceo/ are achieved. The technology thus developed has the highest f/sub T/ in the category of single-polysilicon BiCMOS process ever reported.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126475468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Excess collector current due to an oxide-trapped-charge-induced emitter in irradiated NPN BJTs 在受辐照的NPN BJTs中，由于氧化捕获电荷引起的发射极而产生的过量集电极电流
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587894
A. Wei, S. Kosier, peixiong zhao, W. Combs, M. DeLaus
{"title":"Excess collector current due to an oxide-trapped-charge-induced emitter in irradiated NPN BJTs","authors":"A. Wei, S. Kosier, peixiong zhao, W. Combs, M. DeLaus","doi":"10.1109/BIPOL.1994.587894","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587894","url":null,"abstract":"Excess collector current in irradiated NPN BJTs is linked to an oxide-trapped-charge-induced inversion layer acting as an additional emitter. Excess collector current is modeled by interpreting the inversion layer as an extension of the emitter.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131838111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A physically based model for carrier freeze-out in Si- and SiGe-base bipolar transistors suitable for implementation in device simulators 一种适合在器件模拟器中实现的硅基和硅基双极晶体管载流子冻结的物理模型
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587892
M. Shaheed, C. Maziar
{"title":"A physically based model for carrier freeze-out in Si- and SiGe-base bipolar transistors suitable for implementation in device simulators","authors":"M. Shaheed, C. Maziar","doi":"10.1109/BIPOL.1994.587892","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587892","url":null,"abstract":"A physically based model for carrier freeze-out is presented. This model is implemented in the 2D drift-diffusion simulator PISCES and results of both Si and SiGe base transistor simulations are presented. The new model is shown to provide consistently accurate values for base sheet resistance for a variety of transistors over a wide range of temperatures.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133827111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A fully compensated active pull-down ECL circuit with self-adjusting driving capability 具有自调节驱动能力的全补偿有源下拉ECL电路
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587875
K. Ueda, N. Sasaki, Hisayasu Sato, K. Mashiko
{"title":"A fully compensated active pull-down ECL circuit with self-adjusting driving capability","authors":"K. Ueda, N. Sasaki, Hisayasu Sato, K. Mashiko","doi":"10.1109/BIPOL.1994.587875","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587875","url":null,"abstract":"An active pull-down ECL circuit with full compensation for voltage and temperature is proposed. This circuit adjusts its pull-down capability according to its load capacitance. A fair evaluation method to compare the power dissipation of ECL and CMOS circuits is also proposed.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121225659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Silicon bipolar 14 Gb/s 1:4-demultiplexer IC regarding system requirements 硅双极14gb /s 1:4解复用IC，满足系统要求
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587871
Z. Lao, U. Langmann, J. Albers, E. Schlag, D. Clawin
{"title":"Silicon bipolar 14 Gb/s 1:4-demultiplexer IC regarding system requirements","authors":"Z. Lao, U. Langmann, J. Albers, E. Schlag, D. Clawin","doi":"10.1109/BIPOL.1994.587871","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587871","url":null,"abstract":"A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems, has been designed based on a 21 GHz f/sub T/ 0.4 /spl mu/m Si bipolar process. It operates up to 14 Gb/s (14 GHz) with a phase margin of 250/spl deg/. The power consumption is 2 W with a -4.5 V supply.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128401376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A double-polysilicon self-aligned npn bipolar process (ADRF) with optional NMOS transistors for RF and microwave applications 一种双多晶硅自对准npn双极工艺(ADRF)，可选用于射频和微波应用的NMOS晶体管
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587899
K. O, P. Garone, C. Tsai, B. Scharf, M. Higgins, D. Mai, C. Kermarrec, J. Yasaitis
{"title":"A double-polysilicon self-aligned npn bipolar process (ADRF) with optional NMOS transistors for RF and microwave applications","authors":"K. O, P. Garone, C. Tsai, B. Scharf, M. Higgins, D. Mai, C. Kermarrec, J. Yasaitis","doi":"10.1109/BIPOL.1994.587899","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587899","url":null,"abstract":"A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m NMOS transistors with p/sup +/ polysilicon gate for switch applications, lateral pnp transistors, high and low valued resistors, and p/sup +/ polysilicon-to-n/sup +/ plug capacitors, is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers. The RF and microwave capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121072535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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