{"title":"30 GHz双极f/sub / T/单聚BiCMOS技术","authors":"C. Wang, J. Van Der Velden","doi":"10.1109/BIPOL.1994.587902","DOIUrl":null,"url":null,"abstract":"We present process design and device performance of bipolar transistors embedded in a single-poly BiCMOS technology. The bipolar device possesses a CMOS-like morphology and is easily integrated into a CMOS-based process flow with two additional masks. The integrated process yields a structure with minimum topography. Process concerns associated with the conventional double-poly structure are therefore avoided. Shallow emitter and base junction depth are achieved through a conventional ion implantation approach with proper control of the thermal budget. Bipolar transistors featuring 31 GHz bipolar f/sub T/ and 4 V BV/sub ceo/ are achieved. The technology thus developed has the highest f/sub T/ in the category of single-polysilicon BiCMOS process ever reported.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A single-poly BiCMOS technology with 30 GHz bipolar f/sub T/\",\"authors\":\"C. Wang, J. Van Der Velden\",\"doi\":\"10.1109/BIPOL.1994.587902\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present process design and device performance of bipolar transistors embedded in a single-poly BiCMOS technology. The bipolar device possesses a CMOS-like morphology and is easily integrated into a CMOS-based process flow with two additional masks. The integrated process yields a structure with minimum topography. Process concerns associated with the conventional double-poly structure are therefore avoided. Shallow emitter and base junction depth are achieved through a conventional ion implantation approach with proper control of the thermal budget. Bipolar transistors featuring 31 GHz bipolar f/sub T/ and 4 V BV/sub ceo/ are achieved. The technology thus developed has the highest f/sub T/ in the category of single-polysilicon BiCMOS process ever reported.\",\"PeriodicalId\":373721,\"journal\":{\"name\":\"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1994.587902\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1994.587902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
介绍了单聚BiCMOS双极晶体管的工艺设计和器件性能。双极器件具有类似cmos的形态,并且易于集成到具有两个附加掩模的基于cmos的工艺流程中。集成过程产生具有最小地形的结构。因此避免了与传统双聚结构相关的工艺问题。通过传统的离子注入方法,在适当控制热收支的情况下,可以获得较浅的发射极和基极结深度。实现了31 GHz双极f/sub T/和4 V BV/sub ceo/的双极晶体管。由此开发的技术在单多晶硅BiCMOS工艺类别中具有最高的f/sub T/。
A single-poly BiCMOS technology with 30 GHz bipolar f/sub T/
We present process design and device performance of bipolar transistors embedded in a single-poly BiCMOS technology. The bipolar device possesses a CMOS-like morphology and is easily integrated into a CMOS-based process flow with two additional masks. The integrated process yields a structure with minimum topography. Process concerns associated with the conventional double-poly structure are therefore avoided. Shallow emitter and base junction depth are achieved through a conventional ion implantation approach with proper control of the thermal budget. Bipolar transistors featuring 31 GHz bipolar f/sub T/ and 4 V BV/sub ceo/ are achieved. The technology thus developed has the highest f/sub T/ in the category of single-polysilicon BiCMOS process ever reported.