Voltage scalable GHz interface circuits for BiCMOS applications

As technology scales, the operating voltage of IC's will drop and chips on a common board may operate at different power supplies. In such a scenario, it becomes necessary for the high speed interface circuits to be not only compatible with a 3.3 V supply, but also with I/O levels of future chips that operate at even lower voltage supplies. This paper examines basic building blocks in communication designs operating at data rates above 2.5 Gbit/s. Our experimental results show that BiCMOS as a technology can be used to implement circuits operating at 2.5 V and below.