亚纳秒64 Kb BiCMOS SRAM

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI:10.1109/BIPOL.1994.587869

M. Santoro, L. Tavrow, G. Bewick

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引用次数: 2

摘要

本文介绍了一种2K/spl times/32 BiCMOS嵌入式SRAM，其访问时间为900ps。该SRAM使用标准的6T单元与嵌入式访问树相结合，以提高读写速度。SRAM的尺寸与传统的CMOS设计相当。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A subnanosecond 64 Kb BiCMOS SRAM

This paper describes a 2K/spl times/32 BiCMOS embedded SRAM which has an access time of 900 ps. The SRAM uses a standard 6T cell combined with an Embedded Access Tree for improved read and write speeds. The SRAM size is comparable to a conventional CMOS design.

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来源期刊

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting

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