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2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)最新文献

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Processing and Simulation of Output from Lab-on-a-Chip Devices in Cell Mechanical Analysis 芯片实验室设备在细胞力学分析中的输出处理与仿真
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436919
D. Lizanets, R. Walczak
{"title":"Processing and Simulation of Output from Lab-on-a-Chip Devices in Cell Mechanical Analysis","authors":"D. Lizanets, R. Walczak","doi":"10.23919/MIXDES.2018.8436919","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436919","url":null,"abstract":"in this paper we present algorithms and methods used to implement the processing of an image output from lab-an-a-chip devices. Such microdevices are used in the analysis of single biological cells, their characterization and study of their behaviour under different conditions. We mention algorithms of cell detecting, characterization based on their image and automatic distinguishing and tracking in lab-on-a-chips for analysis of sinzle cells. The paper is also devoted to the mechanical simulation of cell deformation under pressure. The model of a light transmittance through deflected cell geometry is presented.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131627333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Qualification of Electronic Systems for Radiation Environments of High Energy Accelerator 高能加速器辐射环境电子系统的鉴定
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436726
S. Uznanski, R. G. Alía, M. Brugger, C. Cangialosi, S. Danzeca, B. Todd
{"title":"Qualification of Electronic Systems for Radiation Environments of High Energy Accelerator","authors":"S. Uznanski, R. G. Alía, M. Brugger, C. Cangialosi, S. Danzeca, B. Todd","doi":"10.23919/MIXDES.2018.8436726","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436726","url":null,"abstract":"Unlike a typical Radiation Hardness Assurance (RHA) methodology, this work presents a system level radiation qualification of a complex electronic system prior to component radiation characterization tests. Such a top-down approach reduces the beam time needed for qualification of components by carefully analyzing failure modes observed on the system level and performing only a subset of component tests for identified cases. This avoids system overdesign, reduces the testing workload and cost by accepting a certain residual failure rate.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133919222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of Pattern Recognition in Myoelectric Signal Using Netlab GLM 基于Netlab GLM的肌电信号模式识别评价
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436881
G. C. Souza, R. Moreno, T. Pimenta
{"title":"Evaluation of Pattern Recognition in Myoelectric Signal Using Netlab GLM","authors":"G. C. Souza, R. Moreno, T. Pimenta","doi":"10.23919/MIXDES.2018.8436881","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436881","url":null,"abstract":"The myoelectric signal that is collected from the surface of the skin can be used to construct rehabilitation systems for people who have suffered some trauma or who were born with some form of malformation. This signal is used to feed classifiers that can tell with some degree of distinction which movement each signal belongs to. Among the approaches used for this task are the use of artificial neural networks (ANN), multi-layer perceptron (MLP), linear discriminant models (LDA), among others. In this study a approach to pattern recognition called Netlab GLM that has two optimized methods for network training is evaluated in different situations. The classical algorithm LDA is used as a criterion of comparison.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114228184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Zener-Based Voltage Reference Design Compensated Using a ΔVBE Stack 基于齐纳的电压基准设计，使用ΔVBE堆栈进行补偿
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436687
Viorel Bucur, Gabriel Banarie, Stefan Marinca, M. Bodea
{"title":"A Zener-Based Voltage Reference Design Compensated Using a ΔVBE Stack","authors":"Viorel Bucur, Gabriel Banarie, Stefan Marinca, M. Bodea","doi":"10.23919/MIXDES.2018.8436687","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436687","url":null,"abstract":"Two temperature insensitive voltage reference types are widely used today, namely buried Zener and bandgap voltage. Reference voltages based on buried Zener diodes are less sensitive to stress and have lower Long Term Drift (LTD) (approx. 3ppm/1kh), but require a minimum supply voltage of at least 6.5V. Bandgap-type voltage references can operate off supply voltages as low as 1V. However, they have larger LTD compared to buried Zener type references (typically $< pmb{30}mathbf{ppm}/pmb{1}mathbf{kh})$. Further enhancements to the architectures presented in [1] and [2] are discussed in this paper. By using a high performance monolithic deep buried Zener and replacing the embedded one, further performance enhancements in the form of lower Re-Flow drift, reduced LTD, better noise and improved linearity characteristics are obtained. Maintaining the overall circuit performance achieved in [1] and [2] of TC approx. 1.5ppm/°C, and max nonlinearity better than ~1mV over the full temperature range from − 40 to 125°C are two critical requirements.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127001046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IP Core of Coprocessor for Multiple-Precision-Arithmetic Computative 多精度算术计算协处理器的IP核
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436868
K. Rudnicki, T. Stefański
{"title":"IP Core of Coprocessor for Multiple-Precision-Arithmetic Computative","authors":"K. Rudnicki, T. Stefański","doi":"10.23919/MIXDES.2018.8436868","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436868","url":null,"abstract":"In this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. The developed digital circuit of the coprocessor works with integer numbers of precision approaching maximally 32 kbits. Our IP core is developed using the very high speed integrated circuit hardware description language (VHDL) and simulated assuming implementation in field-programmable gate arrays (FPGAs). It exchanges data using three 64-bit data buses whereas a code for execution on the coprocessor is fetched from a dedicated 8-bit bus (all buses in AMBA standard - AXI Stream). An instruction set of the coprocessor currently consists of 7 instructions including multiplication, addition and subtraction. The computations can maximally employ 16 registers of the length 32k bits. Simulation results assuming implementation on Zynq system on chip (SoC) show that computations of the factorial $(n!)$ for $n=pmb{1000}$ take $pmb{326.4}mupmb{sec}$. Such a design currently requires 7982 look-up tables (LUTs), 10400 flip-flops (FFs), 33 block RAMs (BRAMs) and 28 DSP modules. The processor is aimed to provide scalability allowing one to use the developed IP core not only in scientific computing, but also in embedded systems employing encryption based on MPA.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130611749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultra Low-power, High-speed Digital Comparator 超低功耗，高速数字比较器
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436901
M. Ghasemzadeh, Saeid Najafibisfar, A. Amini
{"title":"Ultra Low-power, High-speed Digital Comparator","authors":"M. Ghasemzadeh, Saeid Najafibisfar, A. Amini","doi":"10.23919/MIXDES.2018.8436901","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436901","url":null,"abstract":"This paper is appropriated to a novel 64-bit digital comparator with main targets of low-power consumption and minimum delay from the input to the output. The proposed 64-bit digital comparator has been layout in Cadence and Simulation results using HSPICE software with standard $pmb{0.18mu}mathbf{m}$ CMOS technology parameters, demonstrate 2.8GHz and 335ps delay with the power supply of 1.8volt and also Power-Delay Product (PDP) and power consumption are equal to 0.28pj and $pmb{862mu} mathbf{W}$, respectively.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121710677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel, Asynchronous Winner Selection Circuit for Hardware Implemented Self-Organizing Maps 硬件实现自组织映射的并行、异步赢家选择电路
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436891
T. Talaśka, M. Kolasa, R. Dlugosz
{"title":"Parallel, Asynchronous Winner Selection Circuit for Hardware Implemented Self-Organizing Maps","authors":"T. Talaśka, M. Kolasa, R. Dlugosz","doi":"10.23919/MIXDES.2018.8436891","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436891","url":null,"abstract":"The paper presents a novel digital circuit that allows to determine the winning neuron among all neurons in a self-organizing map (SOM), on the basis of their distances to a given input learning pattern. The proposed bit-wise circuit subsequently compares particular bits of the distance signals, starting from the most significant to least significant bits. The overall calculation process is very fast and does not depend on the number of neurons in the SOM. It is only dependent on the resolution of the compared signals. One of the advantages of the proposed solution is its ability to operate with signals distributed at large chip area, without using any clock generator. A prototype circuit comparing 64 signals of the resolution of 6-bits was realized in the CMOS 130 nm process and verified by transistor level simulations. The overall calculation process takes in the worst case 5 ns.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134628446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the Use of Modified Biolek Window for Memristor Modeling in VerilogA 在VerilogA中使用改进的Biolek窗口进行忆阻器建模
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8443592
M. Fino, Tiago Pina
{"title":"On the Use of Modified Biolek Window for Memristor Modeling in VerilogA","authors":"M. Fino, Tiago Pina","doi":"10.23919/MIXDES.2018.8443592","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8443592","url":null,"abstract":"This paper presents the implementation of memristor models in VerilogA. Particular emphasis is given to the modified Biolek memristor model and on its capacity for modeling the nonlinear effects observed in real devices. Results obtained with the implementation of the memristor model using Cadence verilogA compiler are presented.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123467292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
More on Structural Information from Thermal Impedance Measurements in Time Domain 更多关于时域热阻抗测量的结构信息
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436944
F. Masana
{"title":"More on Structural Information from Thermal Impedance Measurements in Time Domain","authors":"F. Masana","doi":"10.23919/MIXDES.2018.8436944","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436944","url":null,"abstract":"Thermal impedance measurement vs. time is one of the standard and well established methods for thermal characterization of semiconductor devices. From such measurements one usually can get behavioral information in the form of data, graphs or models for thermal simulation. Moreover, the results of these measurements contain also structural information about the thermal path that can be very useful in device assembly process characterization and control. Extraction of this kind of information, however, usually requires quite an involved processing of measured data with all the associated calculation burden and numerical errors. This work, following the line of work presented in previous editions of this conference, proposes a method to extract structural information from measured data that provides a better spatial resolution that can be useful in cases of thin substrates like DCB, so common in power module assembly.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124532296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New Model of Solar Cells for SPICE 用于SPICE的新型太阳能电池
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436819
J. Dąbrowski, E. Krac, K. Górecki
{"title":"New Model of Solar Cells for SPICE","authors":"J. Dąbrowski, E. Krac, K. Górecki","doi":"10.23919/MIXDES.2018.8436819","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436819","url":null,"abstract":"In the paper a new compact model of the solar cell is proposed. This model is dedicated for SPICE and it takes into account electrical and thermal phenomena observed in this solar cell and the influence of the angle between the surface of this cell and the ray of light on its characteristics. The form of the elaborated model is described. The measurement set-up used for verification of this model is presented. Some results of measurements and calculations obtained with the use of the proposed model are shown.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124313746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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