Parallel, Asynchronous Winner Selection Circuit for Hardware Implemented Self-Organizing Maps

Abstract

The paper presents a novel digital circuit that allows to determine the winning neuron among all neurons in a self-organizing map (SOM), on the basis of their distances to a given input learning pattern. The proposed bit-wise circuit subsequently compares particular bits of the distance signals, starting from the most significant to least significant bits. The overall calculation process is very fast and does not depend on the number of neurons in the SOM. It is only dependent on the resolution of the compared signals. One of the advantages of the proposed solution is its ability to operate with signals distributed at large chip area, without using any clock generator. A prototype circuit comparing 64 signals of the resolution of 6-bits was realized in the CMOS 130 nm process and verified by transistor level simulations. The overall calculation process takes in the worst case 5 ns.