2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)最新文献

Analysis and Modelling of ICs and Microsystems 集成电路和微系统的分析与建模

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/mixdes.2018.8436711

引用次数: 0

ECG Signal Enhancement with Serial Cascade OWA Filter 用串级OWA滤波器增强心电信号

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436900

T. Pander, T. Przybyla

{"title":"ECG Signal Enhancement with Serial Cascade OWA Filter","authors":"T. Pander, T. Przybyla","doi":"10.23919/MIXDES.2018.8436900","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436900","url":null,"abstract":"Noises which appear during recording of biomedical signal are seldom characterized by the Gaussian distribution, whereas a noise can have an impulsive nature. An application of traditional filtering method at such assumption can lead to introducing a distortion to a filtered signal. In this paper, an overview of the robust filtering problem is provided. The new serial cascade robust filter with application of the ordered weighted aggregation (OWA) operator is proposed. The OWA operator is described applying a weighted average of ordered signal samples in a moving window. By introducing the nonlinear sorting operation and assigning to the sorted samples appropriate values of weights the improvement of filtering in impulsive environment is achieved. The structure of the proposed serial cascade OWA filter consists of two successive OWA filters. The proposed filter is tested with the help of real signal corrupted with an artificial as well as a real noise. The indicator of the filter's performance quality is the root mean square error (RMSE). For testing purpose the electrocardiographic signal is used. The obtained results show that in the field of impulsive noise suppression, the proposed serial cascaded OWA filter lead to better results compared to the reference filters.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123399050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels 集成微通道3D集成电路的热敏感平面规划指南

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436886

P. Zając, M. Galicia, A. Napieralski

引用次数: 0

A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology 基于0.18μm技术的新型半数字低功耗低抖动快速锁相环

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8443590

F. Noruzpur, S. Mahdavi, M. Poreh, S. Ghasemi

引用次数: 1

Compact Modelling for Characterization and Design of Micro-and Nanoelectonic Systems 微纳电子系统表征与设计的紧凑模型

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/mixdes.2018.8436812

引用次数: 0

Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology VeSTIC技术中专用于基本逻辑单元的VeSFET结构优化

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436648

M. Palgan, A. Pfitzner

{"title":"Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology","authors":"M. Palgan, A. Pfitzner","doi":"10.23919/MIXDES.2018.8436648","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436648","url":null,"abstract":"This paper presents a part of feasibility study of VeSTIC (Vertical Slit Transistor-based Integrated Circuit) technology. The goal is an area saving of logic cells designed in this technology by using junction-less VeSFET devices (Vertical-Slit Field-Effect Transistor). Thanks to their feature: two electrically symmetric gates, there is a possibility to greatly reduce the number of elements required to build digital circuits. The use of complementary pair of twin-gate VeSFETs enables to design two-input NOR or NAND cell composed of two instead of four transistors. The combination of the key device parameters: slit width and dopants concentration as well as gate oxide thickness have been established in order to obtain both OR and AND functionality in a single transistor, providing the best distinguishability of the logic states. In particular, we have confirmed that control of the same single bulk channel of VeSFET by two gates ensures to achieve very high drain current ratio (up to le6) corresponding to “11” and “10” input states in the case of the transistor of AND functionality, which is unattainable in other known technologies.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131856136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Nonparametric Spectral Analysis of Periodically Nonstationary Vibration Signals for Electrical Rotary Machines Testing 旋转电机周期性非平稳振动信号的非参数谱分析

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436683

Ihor Javorskyj, Pawel Semcnov, R. Yuzefovych, Zbigniew Zakrzewski

引用次数: 3

Low Complexity Multichannel Neural Data Compression by Exploiting Spatial Signal Correlation 利用空间信号相关性的低复杂度多通道神经数据压缩

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436716

P. Turcza, K. Duda

{"title":"Low Complexity Multichannel Neural Data Compression by Exploiting Spatial Signal Correlation","authors":"P. Turcza, K. Duda","doi":"10.23919/MIXDES.2018.8436716","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436716","url":null,"abstract":"Wireless data transmission accounts for a significant fraction of total power consumed by an implanted high-density microelectrode array neural recording system. It is well known that the problem can be mitigated by using an on-chip data compressor. The suitable data compressor should offer high compression and low signal distortions. In addition it should feature very low power consumption, low memory footprint and low latency. In this paper we evaluate the feasibility of exploiting spatial correlation between neural signals being recorded with closely spaced electrode array for compression purpose. We show that optimal signal decorrelation and compression is possible by linear signal transformation with the matrix obtained with the Principal Component Analysis (PCA). Furthermore, we demonstrate that the optimal PCA based matrix has a similar structure to the Discrete Cosine Transform (DCT) matrix, which is widely used in image compression. Finally, the performance of data compressor exploiting the PCA and the DCT is compared. Along with compression ratio the power consumption and the area of decorrelation processors are reported.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115106020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reflow Oven for Heating and Soldering SMD and BGA Components 回流炉用于加热和焊接SMD和BGA组件

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436841

P. Pawlowski, A. Dabrowski, Marcin Grenz, Michal Bladowski

引用次数: 0

Redundant Double Conversion based Digital Background Calibration of SAR ADC with Convergence Acceleration and Assistance 基于收敛加速和辅助的冗余双转换SAR ADC数字背景标定

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436826

Xiang Ding, K. Hofmann, L. Zhang, Dongbai Yi, Yingjiang Ma

引用次数: 4