A New Semi-Digital Low Power Low Jitter and Fast PLL in 0.18μm Technology

Abstract

This paper presents a new semi-digital low power, low jitter and fast Phase-Locked Loop (PLL). The main advantages of the proposed PLL are to achieve high-speed, to generate non-overlap signal and to consume low power, reliably. The total power consumption of the proposed PLL in frequencies of 150MHz and 400MHz are $\pmb{258. 7\mu\mathrm{W}}$ and $\pmb{638.4\mu\mathrm{W}}$, respectively. Meanwhile, in the maximum frequency (400MHz) the pick to pick and RMS jitter of the suggested structure are 29.95ps and 8.67ps, correspondingly. Also, at the 400MHz and 150MHz the locking time is $\pmb{1.75\mu{\mathrm{s}}}$ and $\pmb{0.814\mu \mathrm{s}}$, respectively. The active area of the PFD and proposed charge pump are $\pmb{9.16\times 5.65\mu\mathrm{m}^{2}}$ and $\pmb{12.15\times 6.45\mu \mathrm{m}^{2}}$ ' respectively. Simulation results of the proposed structure are simulated using the HSPICE BSIM3 model of a standard $\pmb{0.18\mu\mathrm{m}}$ CMOS process.